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73M2901/5V 

Advanced Single 

Chip Modem 

 

11 

DESIGN CONSIDERATIONS 

TDK Semiconductor’s single chip modem solutions 
include all the basic modem functions.  This makes 
these devices adaptable to a variety of applications.   

Unlike digital logic circuitry, modem designs must 
contend with precise frequency tolerances and verify 
low level analog signals, to ensure acceptable 
performance.  Using good analog circuit design 
practices will generally result in a sound design.  
The crystal oscillator should be held to a 50ppm 
tolerance.  Following are additional 
recommendations that should be taken into 
consideration when starting new designs.  

LAYOUT CONSIDERATIONS   

Good analog/digital design rules must be used to 
control system noise in order to obtain high 
performance in modem designs. The more digital 
circuitry present in the application, the more 
attention to noise control is needed.  

High speed, digital devices should be locally 
bypassed, and the telephone line interface and the 
modem should be located next to each other near 
where the telephone line connection is accessed.  It 
is recommended that power supplies and ground 
traces should be routed separately to the analog and 
digital portions on the board.  Digital signals should 
not be routed near low level analog or high 
impedance analog traces.  

The 73M2901/5V should be considered a high 
performance analog  device.  A 10

m

F electrolytic 

capacitor in parallel with a 0.1

m

F Ceramic capacitor 

should be placed between VPD and VND as well as 
between VPA and VNA.  A 0.1

m

F ceramic capacitor 

should be placed between VREF and VNA as well 
as VBG and VNA.  Use of ground planes and large 
traces on power is recommended. 

The 73M2901/5V is the first of a series of parts with 
different and/or additional features. In order to insure 
full lay out compatibility for all the series, it is 
recommended to implement three additional 
resistors in the schematics as shown in the 
recommended schematics arrangement (R11, R12 
and R13). 

TELEPHONE LINE INTERFACE 

Transmit levels at the line are dependent on the 
interface used between the pins and the line.  In 
order to save having to provide external op-amps to 
drive the line coupling transformer, the analog 
outputs (TXAP and TXAN) have the capability to be 
used as the hybrid drivers for connecting to the 

transformer directly (with the required impedance 
matching series resistor).  Used in this configuration, 
there is loss associated in both the receive path and 
transmit path.   

The line interface circuit shown on the following 
page represents the basic components and values

3

 

for interfacing the TDK 73M2901/5V analog pins to 
the telephone line. 

MODEM PERFORMANCE 
CHARACTERISTICS 

The curves presented in this data sheet define 
modem IC performance under a variety of line 
conditions typical of those encountered over public 
service telephone lines.   

BER VS. SNR 

This test represents the ability of the modem to 
operate over noisy lines with a minimum amount of 
data transfer errors.  Since some noise is generated 
in the best dial up lines, the modem must operate 
with the lowest signal to noise ratio (SNR) possible.  
Better modem performance is indicated by test 
curves that are closest to the BER axis.  A narrow 
spread between curves representing the four line 
parameters indicates minimal variation in 
performance while operating over a range of 
aberrant operating conditions.  Typically a DPSK 
modem will exhibit better BER performance test 
curves receiving in the low band (answer mode) 
than in the high band (originate mode).     

BER VS. RECEIVE LEVEL 

This test measures the dynamic range of the 
modem.  Because signal levels vary widely over dial 
up lines, the widest possible dynamic range is 
desirable.  The SNR is held constant at the indicated 
values as the Receive level is lowered from very a 
very high to a very low signal level.  The width of the 
bowl of these curves, taken at the BER point is the 
measure of the dynamic range.  

 

 

                                                             

3

 

TDK73M2901 Demo boards use the line interface shown on the 

following page.  Other designs may have different requirements 
and thus will require different component values or a different 
configuration.  With the shown configuration, there is 
approximately an 8dB loss in the transmit path, and approximately 
a 5dB loss in the receive path. 

Summary of Contents for 73M2901/5V

Page 1: ...ptions for a low power conventional 5 volt design with optional internal hybrid and country specific call progress support FEATURES Low overall system chip count True one chip solution for embedded sy...

Page 2: ...ybrid is to be used the on chip hybrid drivers can be reconfigured to drive a minimum load of 50kW and thus reduce the driver s power consumption The hybrid configuration is controlled by the state of...

Page 3: ...og voltage Analog Supply VNA 21 22 I Negative analog voltage Analog Ground VPD 6 25 29 2 12 27 33 I Positive digital voltage Digital Supply VND 5 22 26 11 24 44 28 I Negative digital voltage Digital G...

Page 4: ...O Serial output to DTE TXCLK 28 31 O Transmit Data Synchronous Clock TXD 27 30 I Serial data input from DTE USR10 12 8 I O This pin can optionally be configured as an active low detect pin This can b...

Page 5: ...ency 11 0592MHz 50ppm Operating Temperature 40C to 85 C TRANSMITTER PARAMETER CONDITIONS MIN NOM MAX UNIT ITU Guard Tone Power 550Hz relative to carrier 1800Hz relative to carrier 5 8 3 5 6 5 2 5 dB d...

Page 6: ...high tone 6 0 DTMF low tone 8 0 DTMF total 3 9 Vref 1 25V VPA 5 0V QAM 9 6 DPSK 7 4 FSK 5 3 DTMF high tone 7 9 DTMF low tone 9 8 DTMF total 5 7 Note The recommended DAA see the TDK 73M2901 Reference M...

Page 7: ...3 dB Intermod Distortion At output TXAP TXAN 1 0kHz 1 2 kHz sine waves summed 2 0Vpk for Vref 1 25V 2 4Vpk for Vref 2 25V Refer to CTR21 specification for complete description of requirements sum of u...

Page 8: ...ISTICS PARAMETER SYMBOL CONDITION MIN NOM MAX UNIT Input Low Voltage Except OSCIN RESET VIL 0 5 0 2Vcc V Input Low Voltage OSCIN RESET VIL 0 5 0 2 Vcc V Input High Voltage Except OSCIN RESET VIH 0 5 V...

Page 9: ...m Digital Power Supply 5V IDDd 30pF pin 31 37 mA Maximum Analog Power supply 5V HBDEN pulled high IDDah1 30pF pin 20 25 mA Maximum Analog Power Supply 5V HBDEN pulled low IDDah0 30pF pin 4 6 mA Maximu...

Page 10: ...The firmware will automatically enter a power saving idle mode if the modem is on hook and there are no incoming host commands The modem automatically powers up upon receiving the next command This p...

Page 11: ...dependent on the interface used between the pins and the line In order to save having to provide external op amps to drive the line coupling transformer the analog outputs TXAP and TXAN have the capa...

Page 12: ...1 2901_P32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ASRCH RING RELAY RI VND VPD DCD DSR CTS RTS USR11 USR10 LIU RST HBDEN VPA TXAN TXAP VREF VBG RXA VNA V...

Page 13: ...73M2901 5V Advanced Single Chip Modem 13 TYPICAL USA APPLICATION SCHEMATICS...

Page 14: ...002A Line 5 0V 25C 1 00E 00 1 00E 01 1 00E 02 1 00E 03 1 00E 04 4 10 11 12 13 14 15 16 17 18 19 8 12 16 20 24 28 32 36 40 44 1 00E 05 1 00E 06 1 00E 00 1 00E 01 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 0...

Page 15: ...LK 13 RESET 29 VPD 14 HBDEN 30 RXD 15 VPA 31 RXCLK 16 TXAN 32 DTR 44 PIN TQFP PIN OUT PIN PIN NAME PIN PIN NAME PIN PIN NAME PIN PIN NAME 1 N C 12 VPD 23 N C 34 N C 2 VPD 13 N C 24 VND 35 RXD 3 DCD 14...

Page 16: ...73M2901 5V Advanced Single Chip Modem 16 MECHANICAL DRAWINGS 32 Pin PLCC...

Page 17: ...73M2901 5V Advanced Single Chip Modem 17 MECHANICAL DRAWINGS continued 44 Pin TQFP JEDEC LQFP...

Page 18: ...infringements of patents and trademarks or other rights of third parties resulting from its use No license is granted under any patents patent rights or trademarks of TDK Semiconductor Corporation and...

Page 19: ...73M2901 5V Advanced Single Chip Modem 19 August 22 2001 Removed 5V pin callouts from package drawing August 30 2001 Updated Mechanical Drawing...

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