INSTRUCTION MANUAL
CCG
TDKLambda
<Page>
12/23
63. Maximum Output Ripple and Noise
This output ripple and noise voltage is measured at connection as shown in Fig.64.
Connect ceramic capacitor (C2, C3 : 22
μ
F) at 50mm distance from the output terminal.
Measure at C2 terminals as shown in Fig.64 using coaxial cable with JEITA attachment.
Use oscilloscope with 20MHz frequency bandwidth or equivalent.
Fig.64 Measurement of Maximum Output Ripple and Noise
Take note that, PCB wiring design might influence output ripple voltage and spike noise voltage.
Generally, increasing capacitance value of external capacitor can reduce output ripple voltage and
connecting ceramic capacitor can reduce output spike noise voltage.
Note1
）
When using 3.3V and 5V output models of CCG30S below
20ºC ambient temperature
, u
se
two ceramic capacitors in parallel to reduce ESR.
Note1)
+
C2
50mm
As short as possible
+Vout
Vout
CCGD
C2, C3 : 22μF Ceramic Capacitor
Oscilloscope
JEITA attachment
R:50Ω
C:4700pF
R
C
1.5m 50Ω
Coaxial Cable
R
C
1.5m 50Ω
Coaxial Cable
JEITA attachment
R:50Ω
C:4700pF
C3
Load
+
Load
COM
Load
+
C2
50mm
As short as possible
+Vout
Vout
CCGS
C2 : 22μF Ceramic Capacitor
Oscilloscope
JEITA attachment
R:50Ω
C:4700pF
R
C
1.5m 50Ω
Coaxial Cable
