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8. Timing Chart
]
●
Pixel clock timing (common in various operation modes)
[Phase relationship between clock output and data]
CH2 :10bit
CH1: 10bit
10ns (max)
CLK
Clo ck ou tput
1 CLK=33 .3 nS
Dig ital data
DEMULTIPLEX.
A /D
10bit
CH 1
( LDV, FDV)
P CLK
1/2
1 0/8bit
CLK
CH 2
1 0/8bit
C
h
a
n
n
e
l
L
in
k
C
a
m
e
ra
L
in
k
B
a
s
e
C
o
n
fi
g
u
ra
ti
o
n
Cam era Link
conne ctor
(Note) The above timing represents the signal timing before being encoded to serial data by the channeling device on the
side of the sending end (the part circled in the above right figure). If signal conversion from serial to parallel is made by
a channel link device in accordance with the standard of Camera Link on the side of the receiving end, the phase
relationship between the clock and the data after decoding will be different from that of the above timing due to the
structural nature of a channel link device. (In the case of the output from a channel link device, the data are aligned
with the trailing edge of the clock signal.) As a general rule, this variation in timing is correctly adjusted at the capture
timing of a capture board, the equal definition file to that of the conventional parallel output type can be used for
capturing.
(!)
8 or 10 bit x 2 tap output with 30MHz clock is employed for FS5100SPL. Therefore, there is no compatibility with the
FC5100CL and a dedicated configuration file is required.
(Note) When a channel link device is mounted directly to the capture interface on the user side, instead of using a
commercially available capture board that supports Camera Link, it is necessary to pay close attention to the
descriptions of the data sheet of the channel link device including the phase relationship between data and clock prior to
the use.
●
Horizontal timing
ＨＤ
１５ ０
１hor izo ntal ti me （ １Ｈ ）
（
Internal horizontal
syncronous signal
）
３ １ ９ ２
Digital output
(CH
1,2
)
Effec tiv e image duration
(
1224
×
2 pix els )
１２ ２ ４Ｃ
ＬＤＶ
CCD output signa l
Horiz ontal trans fer
s us pens ion time
D
u
m
m
y
b
it
ト
Ｏ Ｂ
４ ０
６ １ ５
４
Effec tiv e pix els
２ ４ ４８
１
６５ ９
１ ２
４
３
５
１
２
４
４
４
２
４
４
５
２
４
４
７
２
４
４
６
２
４
４
８
４０ １
４
Ｏ
Ｂ
４ ０
ＣＬＫ
１ Ｃ
（ ２）
1
2
3
4
24 47
24 48
244 5
244 6
244 3
244 4
244 1
244 2
2 439
2 440
5
6
7
8
9
10
１
１ １２ Ｃ
１ ８０ Ｃ
１ ６５ Ｃ
* Unless otherwise specified, the time unit of the numbers in the horizontal timing chart is CLK (= 1/60.00MHz = 16.7nS).
Also, CLK output ;1C =1/30.00MHz = 33.3nS
* The numbers shown here are design values, and the actual equipment should be checked for the details.