Tait TP9100, Service Manual, Page: 45 / 326

TP9100 Service Manual
Description 45
© Tait Electronics Limited May 2005
The FCL generates an output of 13.012MHz±4kHz. Initially a voltage
controlled crystal oscillator (VCXO) produces a quasi-regulated frequency in
the required range. The VCXO output is fed to a mixer where it is mixed with
the 13.000MHz TCXO frequency. The mixer, after low-pass filtering to
remove unwanted products, produces a frequency of 12kHz nominally. This is
converted to digital form and transported to the frequency control block in the
custom logic.
The frequency control block compares the mixer output frequency to a
reference generated by the digital clock and creates a DC error signal.
A programmed offset is also added. This error signal is converted to analog
form and used to control the VCXO frequency and reduce the initial error.
Once settled, the loop “locks” to the TCXO frequency with a programmed
offset frequency. The FCL output therefore acquires the TCXO's frequency
stability.
The FCL may be run in an open-loop configuration for short durations to
increase the response time of the power-save modes.
Modulation
The full bandwidth modulation signal is obtained from the DSP in digital
form at a sample rate of 48 kHz. In traditional dual-point modulation
systems the modulation is applied, in analog form, to both the frequency
reference and the VCO in the RF PLL, combining to produce a flat
modulation response down to DC. Reference modulation is usually applied
directly to the TCXO.
The frequency reference is generated by the FCL, which itself requires dual-
point modulation injection to allow modulation down to DC. With another
modulation point required in the RF PLL, this system therefore requires
triple-point modulation. The modulation signals applied to the FCL are in
digital form while for the RF PLL (VCO) the modulation signal is applied
in analog form. The modulation cross-over points occur at approximately
30 and 300Hz as determined by the closed loop bandwidths of the FCL and
RF PLL respectively.
Frequency
Generation
The RF PLL has a frequency resolution of 25 kHz. Higher resolution
cannot be achieved owing to acquisition-time requirements and so for any
given frequency the error could be as high as ±12.5 kHz. This error is
corrected by altering the reference frequency to the RF PLL. The FCL
supplies the reference frequency and is able to adjust it up to ±300ppm with
better than 0.1ppm resolution (equivalent to better than 50 Hz resolution at
the RF frequency). The FCL offset will usually be different for receive and
transmit modes.
Fast Frequency
Settling
Both the FCL and RF PLL employ frequency-acquisition speed-up
techniques to achieve fast frequency settling. The frequency-acquisition
process of the FCL and RF PLL is able to occur concurrently with minimal
loop interaction owing to the very large difference in frequency step size
between the loops.