Tadpole SPARCbook 3 series, Reference Manual

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11-2
Display Interface
Display Interface Overview
11.1 Display Interface Overview
11.1.1 Architecture
The display interface, illustrated in Figure 11-1, is based around two major
components, the Weitek Power 9100 User Interface Controller and an IBM
RGB528 palette DAC (RAMDAC). These provide advanced graphics
functions and all timing and control signals required to control 2 MBytes of
dual ported Video RAM (VRAM), which functions as frame buffer
memory, and to drive the internal and external displays.
The Power 9100 provides the host interface between the SBus and the
frame buffer, providing accelerated graphics operations for 8, 16 and 32
bits per pixel.
The frame buffer comprises four 256K x 16 bit page mode VRAM devices,
although these appear to the Power 9100 hardware as eight 256K x 8 bit
devices. These are organized to into a 2 Mbyte array to provide storage for
image data.
Figure 11-1 SPARCbook 3 Display Interface Architecture
Serial
Access
Port
Random
Access
Port
Weitek
64-bit
Pixel Data
Data
Address
VRAM Controls
MD(23:16)
Register Selects
VGA(7:0)
Digital Video
RGB Video
IBM528
Power 9100
Palette
DAC
S3GX_TRMBook Page 2 Friday, September 19, 1997 11:39 am