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SC-TDC-1100 Series Manual
4 TDC Layout
4.1 Schematic Description
The design of the SC-TDC-1100 series combines the excellent performance of the GPX TDC chip with a
high speed USB interface.
A field programmable gate array (FPGA) enables comfortable setups and a variable data stream handling
from the TDC via USB.
The main delayline detector readout functionality is permanently programmed. A complex FIFO design
makes data losses almost impossible. The user DLL controls the data handling and streaming for the user.
The following brief description of the internal structure of the measurement unit is only informative:
Figure 2: Schematic sketch of TDC functioning.
Arrival times of pulses at the stop inputs are measured by the TDC with respect to either an internal
reference start signal, provided by the FPGA, or an external start signal. An internal electronics provide the
TDC start signal to an additional BNC socket for further extended measurement use. The measurement
dwell times for data from the TDC are settled within the FPGA by a quartz stabilized time gate in an interval
from 1ms to 1193h.
The synchronization pulse for the external acquisition start (Sync. In) is transferred directly into the FPGA
that controls the acquisition process. The FPGA also sends out a synchronization pulse for marking the end
of an acquisition (via the Sync. Out socket).
SC-TDC-1100 Series Manual | Surface Concept GmbH
