Supero X9SRG-F, User Manual

Page: 51 / 107

Chapter 2: Installation
2-25
JI2C1
1
JPW
1
1
11
10
20
JUIDB1
1
2
JPW2
5 8
4
1
JPW3
5 8
4 1
JLAN
2
JLAN
1
JSD1
1
3
J1
3
JPCIE3
JPCIE1
JPCIE2
12
7
8
1
2
7
8
2 8
JST
BY
1
3
1
JIPM
B1
X9SRG
RE
V:
1.00
DESIGNED IN USA
MH
5
JD1
7
SATA6
1 7
SATA5
1 7
SATA4
7 1
SATA3
7 1
JF
1
20 19
2 1
SAS3
7 1
SAS1
1 7
SAS2
7 1
SATA2
1 7
SATA1
7 1
SAS4 7
1
A
J17
SP
1
+
JBT1
LED2
A
C
LE2
C
A
LE1
A
C
BD1
AC
BT
1
JOH1
J28
1
JL1
1
C509
JVGA
1
JTPM1 1
2
19
20
J26
1
2
7
J2
3
1
2
7
JCOM1
FAND
1
FANC
4 1
FANB 4 1 FANA 4 1
FAN4 1
4
FA
N1
1
FA
N3
4
1
FA
N2
4 1
J6
J5
J12
J7
J4
J2
J3
J1
JI2C3 3 1
JI2C2 1
3
JPL1
1
3
JPL2 1
3
JW
D
JP
ME1
3
1
JPB1
3
JPG1
3
1
JPR1:
1-2:NORMAL 2-3:BIOS RE
CO
VE
RY
1-2:NORMA
L
2-3:ME RE
CO
VE
RY
SLOT3 PCIE 3.0X8
SXB2
B
SXB2
A
SXB1A
US
B
JBT1:CMOS CLEAR
JSD1: PWRSDO
M
PW
R
JF
1
ON
FA
IL
RS
TP
S
2
NIC
1
NIC
LED UI
D
LED
LED PW
R
HD
DX
NM
I
DIMMA1
2-3:NM
I
1-2:RST(DE
FA
UL
T)
JWD:
WA
TC
H DOG
TIMER
LAN
1
LAN2
UI
D
JI2C2/JI2C3 1-2:Enable 2-3:Disabl
e
WRITE PR
OT
EC
T
JWP1
:
JOH1:OVER HEA
T LED
US
B
SXB1B
1-2:RST 2-3:NIM
I
JWD:
2-3:DISABLE 1-2:ENABLE JPL2:LAN
2
2-3:DISABLE 1-2:ENABLE JPL1:LAN
1
JP
MB
:CHASSIS INTRUSION
JL1
I-SATA4 I-SATA2
DIMMC1
I-SATA3
I-SATA0
VG
A
I-SATA5 I-SATA1
COM1
USB/0/1
JD1: 4-7:SPEAKER 1-2:PWR_LED
OF
F:
Disabl
e
JP
ME1:
JI2C1 ON:Enabl
e
2-3:DISABLE 1-2:ENABLE JPB1: BMC
2-3:Disabl
e
1-2:Enable JPG1:
VG
A
CPU
JTPM1: TPM/PORT80
JST
BY
1:ST
AND
BY
POWER FOR DO
M
C
Serial Link General-Purpose Headers
(SGPIO)
Pin Definitions
Pin# Definition Pin Definition
1 NC 2 NC
3 Ground 4 DATA Out
5 Load 6 Ground
7 Clock 8 NC
A. T-SGPIO1
B. T-SGPIO2
C. T-SGPIO-S
D. TPM Header
A
B
T-SGPIO1/2/-S Headers (T-SGPIO)
Four T-SGPIO (Serial-Link General
Purpose Input/Output) headers are
located next to the I-SATA Ports on
the motherboard. These headers are
used to communicate with the enclo-
sure management chip in the system.
See the table on the right for pin
definitions. Refer to the board layout
below for the locations of the headers.
Trusted Platform Module Header (JTPM1)
Pin Definitions
Pin # Definition Pin # Definition
1 LCLK 2 GND
3 LFRAME# 4 No Pin
5 LRESET# 6 +5V (X)
7 LAD3 8 LAD2
9 3.3V 10 LAD1
11 LAD0 12 GND
13 SMB_CLK4 14 SMB_DAT4
15 +3V_DUAL 16 SERIRQ
17 GND 18 CLKRUN# (X)
19 LPCPD# 20 LDRQ# (X)
TPM Header (JTPM1)
This header is used to connect a
Trusted Platform Module (TPM),
which is available from a third-party
vendor. A TPM is a security device
that supports encryption and authen-
tication in hard drives. It enables the
motherboard to deny access if the
TPM associated with the hard drive
is not installed in the system. See the
table on the right for pin definitions.
D