Chapter 2: Installation
2-23
Power Button
OH/Fan Fail/PWR
FaiL/UID LED
1
NIC1 Link LED
Reset Button
2
Power Fail LED
HDD LED
FP PWRLED
Reset
PWR
3.3 V
ID_UID_SW/3/3V Stby
Blue LED Cathode
Ground
Ground
19
20
3.3V
X
Ground
NMI
X
NIC2 Link LED
NIC2 Activity LED
NIC1 Activity LED
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin definitions.
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin definitions.
NMI Button
Pin Definitions (JF1)
Pin# Definition
19
Control
20
Ground
Power LED
Pin Definitions (JF1)
Pin# Definition
15
3.3V
16
PWR LED
Front Control Panel Pin Definitions
A. NMI
B. PWR LED
A
B
J21
BT1
JPW2
FAND
FANB
FANA FAN4
FAN3
FAN2
FANH
FANG
FANE
FANF
FAN1
S_SA
TA0
I-SA
TA0
COM
JSD1
LE4
SW1
JLAN2 JLAN1
JI2C2
JOH1
JSPK1
JL1
JBT1
JPW7
JPW6
JPW5
JPW11
JPW1
DM1
LE1
JPME2
JWD1
J29
JPME1
JPL1
JPG1
T-SGPIO-S
T-SGPIO1
T-SGPIO2
JTPM1
VGA
IPMI LAN
USB/0/1
JI2C1
P2-DIMME1
P2-DIMMF1
P2-DIMMH2
P2-DIMMG2
P1-DIMMC2
P1-DIMMD1
P1-DIMMB2
P1-DIMMA2
PCH SLOT6 PCI-E 2.0 X4 (IN X8)
CPU1 SLOT5 PCI-E 3.0 X8 (IN X16)
P1-DIMMB1
P2-DIMME2
P1-DIMMC1
P1-DIMMA1
P2-DIMMH1
P2-DIMMF2
P1-DIMMD2
P2-DIMMG1
CPU1
CPU2
CPU1 SLOT1 PCI-E 3.0 X16
CPU1 SLOT2 PCI-E 3.0 X16
JF1
USB 8/9
JPB1
FANC
JPW8
CLOSE 1st
OPEN 1st
CLOSE 1st
OPEN 1st
X9DRG-HF+II
Rev. 1.00
BIOS
J30
S_SA
TA1
S_SA
TA2
S_SA
TA3
I-SA
TA1
I-SA
TA2
I-SA
TA3
I-SA
TA4
I-SA
TA5
FPCTRL
BMC
Battery
LAN
CTRL
PCH
JPLD1
CPU2 SLOT3 PCI-E 3.0 X16
CPU2 SLOT4````````````` PCI-E 3.0 X16
