Chapter 1: Introduction
1-9
1-2 Chipset
Overview
The H8DMR-82/H8DMR-i2 serverboard is based on the nVidia MCP55 Pro/NEC
uPD720400 chipset. The nVidia MCP55 Pro functions as Media and Communica-
tions Processor (MCP) and the NEC chip as a PCI-X Tunnel. Controllers for the
system memory are integrated directly into the AMD Opteron processors.
MCP55 Pro Media and Communications Processor
The MCP55 Pro is a single-chip, high-performance HyperTransport peripheral con-
troller. It includes a 28-lane PCI Express interface, an AMD Opteron 16-bit Hyper
Transport interface link, a six-port Serial ATA interface, a dual-port Gb Ethernet
interface, an ATA133/100 bus master interface and a USB 2.0 interface. This hub
connects directly to CPU#1 and through that to CPU#2.
NEC uPD720400
This I/O bridge chip provides two PCI-X domains. Each bridge supports PCI
masters that include clock, request and grant signals. This hub connects to the
MCP55 Pro through a PCI-Express x8 Bus. It also interfaces directly with the
Adaptec SCSI controller.
HyperTransport Technology
HyperTransport technology is a high-speed, low latency point to point link that was
designed to increase the communication speed by a factor of up to 48x between
integrated circuits. This is done partly by reducing the number of buses in the
chipset to reduce bottlenecks and by enabling a more effi cient use of memory in
multi-processor systems. The end result is a signifi cant increase in bandwidth
within the chipset.
