2-26
X8DTN+ User's Manual
JPG1
JPL1
JWD
JF1
JPW4
JPW3
JPW1
Fan1
Fan3
Fan4
Fan8
JWF1
JBT1
LE1
JK1
JWOR1
JL1
JI2C2
JI2C1
JD1
COM1
J11
J100
CPU1Fan
OH LED
CPU2
Floppy
IDE
JP3
USB7
USB6
USB4
SEPC
Slot6 PCI-E2.0 X8
Slot5 PCI-E X4
Slot4 PCI-E2.0 X8
Slot3 PCI-X 133MHZ
Slot2 PCI-X 100/133MHZ
Slot1 PCI-X 100/133MHZ
LAN2
VGA
KB/MS
Clear CMOS
IPMB
I-SA
TA
0
PWR I2C
Fan7
CPU2 Fan
XDP
CPU1
USB0/1
T-SGPIO2
T-SGPIO1
LAN1
Slot0 PCI-U
COM2
Fan6
P1 DIMM3A
P1 DIMM3B
P1 DIMM3C
P1 DIMM2A
P1 DIMM2B
P1 DIMM2C
P1 DIMM1A
P1 DIMM1B
P1 DIMM1C
SIMLP
Battery
VGA
CTRL
FP
CTRL
Fan2
P2 DIMM1C
P2 DIMM1B
P2 DIMM1A
P2 DIMM2C
P2 DIMM2B
P2 DIMM2A
P2 DIMM3C
P2 DIMM3B
P2 DIMM3A
J101
J102
J103
J104
J105
J106
J107
J108
Fan5
I-SA
TA
1
I-SA
TA
2
I-SA
TA
3
I-SA
TA
4
I-S
ATA
5
X8DTN+
BIOS
LAN
CTRL
S I/O
Intel 5520
Intel ICH10R
(South Bridge)
PXH
IPMI
SPI
SPKR
JP7
JP5
(North Bridge)
JOH1
Rev
. 2.0
JP6
JPP0
JPP1
JTPM1
TPM Header
JWOL1
A
B
A. Chassis Intrusion
B. T-SGPIO-1
C. T-SGPIO-2
C
T-SGPIO Headers
Two SGPIO (Serial-Link General
Purpose Input/Output) headers
(T-SGPIO-1/T-SGPIO-2) are located
below the fl oppy drive on the mother-
board. These headers support serial
link interfaces for the onboard SATA
connectors. See the table on the
right for pin defi nitions. Refer to the
board layout below for the location.
Note:
NC= No Connections
T-SGPIO
Pin Defi nitions
Pin# Defi nition
Pin Defi nition
1
NC
2
NC
3
Ground
4
Data
5
Load
6
Ground
7
Clock
8
NC
Chassis Intrusion
A Chassis Intrusion header is located
at JL1 on the motherboard. Attach an
appropriate cable from the chassis
to inform you of a chassis intrusion
when the chassis is opened.
Chassis Intrusion
Pin Defi nitions (JL1)
Pin# Defi nition
1
Intrusion Input
2
Ground
Summary of Contents for X8DTN+
Page 1: ...X8DTN USER S MANUAL Revision 1 0c ...
Page 58: ...2 38 X8DTN User s Manual Notes ...
Page 64: ...3 6 X8DTN User s Manual Notes ...
Page 94: ...A 2 X8DTN User s Manual Notes ...
Page 98: ...B 4 X8DTN User s Manual Notes ...