Chapter 1: Introduction
1-9
Introduction
1-2
Chipset Overview
B u i l t u p o n t h e f u n c t i o n a l i t y a n d t h e c a p a b i l i t y o f t h e I n t e l E 7 5 2 0
(Lindenhurst) chipset, The X6DHR-8G2/X6DHR-iG2 motherboard provides
the performance and feature set required for dual processor-based serv-
ers, with configuration options optimized for communications, presentation,
storage, computation or database applications. The Intel E7520 (Lindenhurst)
chipset consists of the following components: the E7520 (Lindenhurst)
Memory Controller Hub (MCH), the ICH5R Controller Hub (ICH), the Intel PCI-
X Hub (PXH).
The E7520 MCH supports single or dual Nocona processors with Front Side
Bus speeds of 800 MHz. Its memory controller provides direct connection to
two channels of registered DDRII with a marched system bus address and
data bandwidths of up to 6.4GB/s. The E7520 also supports the new PCI-
Express high speed serial I/O interface for superior I/O bandwidth. The MCH
provides three configurable x8 PCI Express interfaces which may alterna-
tively be configured as two independent x4 PCI Express interfaces. These
interfaces support connection of the MCH to a variety of other bridges that
are compliant with the PCI Express Interface Specification, Rev. 1.0a, such
as 82546GB GLAN Adaptor, H/W RAID controllers and TCP/IP Off-load en-
gines. The MCH interfaces with the ICH5R I/O Controller Hub (ICH5) via a
dedicated Hub Interface supporting a peak bandwidth of 266 MB/s using a
x4 base clock of 66 MHz. The PXH provides connection between a PCI
Express interface and two independent PCI bus interfaces that can be con-
figured for standard PCI -X 1.0 protocol.
ICH5R System Features
In addition to providing the I/O subsystem with access to the rest of the
system, the ICH5R I/O Controller Hub integrates many I/O functions.
The ICH5R I/O Controller Hub integrates: 2-channel Ultra ATA/100 Bus Mas-
ter IDE Controller, two Serial ATA (SATA) Host w/RAID0, RAID1 support,
SMBus 2.0 Controller, LPC/Flash BIOS Interface, PCI 2.2 Interface and Sys-
tem Management Controller.
