4-12
S
UPER X5DPA-8GG
User’s Manual
ICH3 Dev29 Func1, USB#2
Select "Enabled" to enable the ICH3 USB Host Controller#2. The options are
"
Disabled
" and "Enabled."
ICH3 Dev29 Func2, USB#3
Select "Enabled" to enable the ICH3 USB Host Controller#3. The options are
"
Disabled
" and "Enabled."
ICH3 Positive Decode
Select "Enabled" to activate the function of Positive Decode in ICH3. Select
"Enabled" only when the optional Onboard PCI/ISA Bridge is present. The
options are "
Disabled
" and "Enabled."
IOAPIC
Select "Enabled" to enable IOAPIC in ICH3. The options are "
Enabled
" and
"Disabled."
Extended IOAPIC
Select "Enabled" to enable the extended mode of IOAPIC in ICH3. The op-
tions are "
Enabled
" and "Disabled."
CPU B.I.S.T.
Select "Enabled" to enable the function of CPU Built In Self Test. The options
are "
Enabled
" and "Disabled."
!
Intel ICH3 SouthBridge Configuration
This feature allows the user to configure the settings for Intel ICH3
SouthBridge chipset.
ICH3 Dev31 Func1, IDE
Select "Enabled" to enable the ICH3 IDE Controller. The options are "
En-
abled
" and "Disabled."
ICH3 Dev31 Func3, SMBUS
Select "Enabled" to enable the ICH3 SMBUS Controller. The options are "
En-
abled
" and "Disabled."
ICH3 Dev29 Func0, USB#1
Select "Enabled" to enable the ICH3 USB Host Controller#1. The options are
"
Enabled
" and "Disabled."