2-20
SUPER X5DPA-8GG User's Manual
VGA Enable/Disable
JP4 allows you to enable or disable
the VGA port. The default position
is on pins 1 and 2 to enable VGA.
S e e t h e t a b l e o n t h e r i g h t f o r
jumper settings.
Jumper
Position
1-2
2-3
Definition
Enabled
Disabled
VGA Enable/Disable
Jumper Settings
(JP4)
GLAN Enable/Disable
Change the setting of JP3 to
enable or disable the onboard
GLAN1. Change the setting of
JP6 to enable or disable the
onboard GLAN2. See the table
on the right for jumper
settings. The default setting is
enabled.
Jumper
Position
Pins 1-2
Pins 2-3
Definition
Enabled
Disabled
LAN
Enable/Disable
Jumper Settings
(JP3: LAN 1, JP6: LAN2 )
DIMM #2B
DIMM #2A
DIMM #1B
DIMM #1A
BANK 2
BANK1
ATX PWR CONN
J15
VGA
CPU 2
BK Panel USB 0/1
Keyboard
Mouse
CPU 1
GLAN1
GLAN2
Chassis
Fan5
CPU Fan2
KeyLock
SW
IPMI SOCKET
SMB
P64H2-
MCH
100 MHz PCI-X #1
Floppy
SUPER
IO
®
CPU Fan1
BATTERY
PWR LED/SPKR
FORCE
PW ON
Serial
Port
100 MHz PCI-X #2
JP6
Pin 1
Pin 1
JP3
Clear CMOS
Pin 1
Pin 1
Pin 1
IDE 1
IDE 2
JF2
INTEL
RC82541
SSI 24PIN
INTEL
RC82541
FPUSB0/1/2
J L 1
JBT1
USB2
JP37
ICH3
FWH-
BIOS
JP39
Pin 1
-NORTH
BRIDGE
CH Fan4
J D 1
SU
PER
X
5D
PA
4-PIN PW CONN
8-PIN PW CONN
WOL1
JP32
J
W
O
R
1
PCI BRIDGE
-SOUTH
BRIDGE
JP40
Speaker
SP1
J6
Pin 1
Ultra III LVD Channel B
Ultra III LVD Channel A
J
A
1
J A 2
JPA2
Pin 1
R
A
G
E
J
A
4
X
L
Pin 1
J
P
4
J 2 7
J D 2
J 2
J 3
COM 2
J
2
6
J
P
A
1
WD
Adaptec
7 9 0 2 W
(SCSI)
J
P
3
5
JP7
P64H2-
®
PWR LED/SPKR
100 MHz PCI-X #2
JP6
Pin 1
Pin 1
JP3
Clear CMOS
Pin 1
JBT1
J D 1
S
U
P
E
R
X
5
W
PCI BRIDGE
Speaker
SP1
Ultra III LVD Channel B
Ultra III LVD Channel A
JA1
J A 2
JPA2
Pin 1
RAGE
JA4
XL
Pin 1
JP
A
1
Adaptec
7 9 0 2 W
(SCSI)
Floppy
PWR LED/SPKR
Clear CMOS
Pin 1
Pin 1
Pin 1
FPUSB0/1/2
J L 1
JBT1
USB2
J D 1
WOL1
JP32
JWOR1
Ultra III LVD Channel B
III LVD Channel A
JA1
J A 2
JPA2
RAGE
J
A
XL
Pin 1
JP4
J 2 7
J D 2
J 2
J 3
(SCSI)
JP7
GLAN Enable/Disable
VGA Enable/Disable