Chapter 1: Introduction
1-13
Introduction
1-2
Chipset Overview
The Intel E7501 chipset is a high-performance chipset with a performance
and feature-set designed for mid-range, dual processor servers. The
E7501 chipset consists of four major components: the Memory Controller
Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0 (P64H2)
and the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and
three for high-speed I/O communications. The MCH employs a 144-bit wide
memory bus for a DDR-266 memory interface, which provides a total band-
width of 4.2 GB/s (3.2 GB/s for DDR-200). The ICH3 interface is a 266 MB/
sec point-to-point connection using an 8-bit wide, 66 MHz base clock at a
4x data transfer rate. The P64H2 interface is a 1 GB/s point-to-point con-
nection using a 16-bit wide, 66 MHz base clock at a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including
a two-channel UDMA100 bus master IDE controller, USB host controllers, a
System Management Bus controller and an AC'97 compliant interface.
Each of the P64H2 PCI-X Hubs (two on the X5DP8-G2, X5DPE-G2 and X5DPi-
G2 and one on the X5DPR-8G2+ and X5DPR-iG2+) provides a 16-bit con-
nection to the MCH for high-performance IO capability and two 64-bit PCI-X
interfaces.
1-3
Special Features
ATI Graphics Controller
The X5DP8-G2/X5DPE-G2/X5DPR-8G2+/X5DPR-iG2+/X5DPi-G2 has an inte-
grated ATI video controller based on the Rage XL graphics chip. The Rage
XL fully supports sideband addressing and AGP texturing. This onboard
graphics package can provide a bandwidth of up to 512 MB/sec over a 32-
bit graphics memory bus.
Recovery from AC Power Loss
BIOS provides a setting for you to determine how the system will respond
when AC power is lost and then restored to the system. You can choose
for the system to remain powered off (in which case you must hit the
power switch to turn it back on) or for it to automatically return to a power-
Summary of Contents for X5DP8-G2
Page 9: ...Chapter 1 Introduction 1 3 Introduction Notes ...
Page 46: ...2 22 SUPER X5DP8 G2 DPE G2 DPR 8G2 DPR iG2 DPi G2 User s Manual Notes ...
Page 52: ...3 6 SUPER X5DP8 G2 DPE G2 DPR 8G2 DPR iG2 DPi G2 User s Manual Notes ...
Page 76: ...4 24 SUPER X5DP8 G2 DPE G2 DPR 8G2 DPR iG2 DPi G2 User s Manual Notes ...
Page 82: ...A 6 SUPER X5DP8 G2 DPE G2 DPR 8G2 DPR iG2 DPi G2 User s Manual Notes ...
Page 88: ...B 6 SUPER X5DP8 G2 DPE G2 DPR 8G2 DPR iG2 DPi G2 User s Manual Notes ...