52
Super X11DPX-T User's Manual
Trusted Platform Module/Port 80 Header
Pin Definitions
Pin#
Definition
Pin#
Definition
1
P3V3
2
SPI_TPM_CS_N
3
PCIE_RESET_N#
4
SPI_PCH_MISO
5
SPI_PCH_CLK#
6
Ground
7
SPI_PCH_MOSI
8
N/A
9
JTPM1_P3V3A
10
IRQ_TPM_SPIN_N
TPM Header
The JTPM1 header is used to connect a Trusted Platform Module (TPM)/Port 80, which is
available from SMCI (optional). A TPM/Port 80 connector is a security device that supports
encryption and authentication in hard drives. It allows the motherboard to deny access if the
TPM associated with the hard drive is not installed in the system. See the table below for
pin definitions.
1. TPM/Port 80 Header
2. Chassis Intrusion
COM1
LAN
CTRL
DESIGNED IN USA
X11DPX-T
REV:1.01A
I-SATA4~7 I-SATA0~3
FANC
FAND
CPU2
CPU1
BIOS
LICENSE
JBT1
M.2 CONNECTOR
SAN MAC
MAC CODE
JF1
BAR CODE
IPMI CODE
VGA
USB 2/3
BT1
JNVI2C2
JNVI2C1
PCH
FANA FAN2
FAN5
FAN1
P2-DIMMC1
P2-DIMMB1
P2-DIMMA1
P2-DIMMA2
P2-DIMMD2
P2-DIMMD1 P2-DIMME1
P2-DIMMF1
FAN6
P1-DIMMA2
P1-DIMMA1
P1-DIMMB1
P1-DIMMC1
JPWR1
JPWR2
JPWR3
JPI2C1
FAN4
LEDBMC
S-UM12
S-SATA0
S-SATA1
FANB
FAN3
JNCSI1
S-SGPIO
JSTBY1
JWD1
JSEN1
COM2
P1-DIMMF1
P1-DIMME1
P1-DIMMD1
P1-DIMMD2
SP1
USB8 (3.0)
JTPM1
JPWR4
ALWAYS POPULATE DIMMx1 FIRST
ALWAYS POPULATE DIMMx1 FIRST
ALWAYS POPULATE DIMMx1 FIRST
ALWAYS POPULATE DIMMx1 FIRST
JUIDB1
(UID)
LED2
(UID-LED)
USB 6/7 (3.0)
JL1
LEDPWR
JSD1
JSD2
JIPMB1
JRK1
JPTG1
JPCIE1
1
(CPU2 SLOT1
1 PCI-E 3.0 x4 (IN x8))
JPME2
LAN 2
LAN 1 USB 0/1 IPMI_LAN
USB 4/5 (3.0)
BMC
JPCIE2
(CPU1 SLOT2 PCI-E 3.0 x16)
JPCIE1
(CPU1 SLOT1 PCI-E 3.0 x8)
JPCIE3
(CPU1 SLOT3 PCI-E 3.0 x8)
JPCIE6
(CPU2 SLOT6 PCI-E 3.0 x16)
JPCIE5
(CPU2 SLOT5 PCI-E 3.0 x8)
JPCIE7
(CPU1 SLOT7 PCI-E 3.0 x8)
JPCIE8
(CPU2 SLOT8 PCI-E 3.0 x16)
JPCIE4
(CPU1 SLOT4 PCI-E 3.0 x16)
JPCIE9
(CPU2 SLOT9 PCI-E 3.0 x8)
JPCIE10
(CPU2 SLOT10 PCI-E 3.0 x8)
1
2
Chassis Intrusion
Pin Definitions
Pins
Definition
1
Intrusion Input
2
Ground
Chassis Intrusion
A Chassis Intrusion header is located at JL1 on the motherboard. Connect an appropriate
cable from JL1 to the chassis so that you can be informed of a chassis intrusion (via IPMI)
when the system case is opened. Refer to the table below for pin definitions.