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Chapter 2: Installation
CPLD Header
The Complex Programmable Logical Device (CPLD) header is located on JP2 on the
motherboard. Connect an appropriate cable to use this feature.
BAR CODE
BIOS
LICENSE
IPMI CODE
BP
PWR2
BP
PWR1
P1-DIMMC1
I-SATA4~7
P1-DIMMB2
I-SATA0~3
P1-DIMMB1 P1-DIMMC2
P1-DIMMA1
P1-DIMMA2
CPU1_POR
T2C
SXB3B
JWD1
CPU1_POR
T3C
CPU1_POR
T3A
CPU1_POR
T2A
SXB3C
CPU1_POR
T1A
SXB3A
P1-DIMMD2
P1-DIMMD1P1-DIMME2
P1-DIMME1
P1-DIMMF1 P1-DIMMF2
USB0/1(3.0)
CPU2
CPU1
BATTERY
COM1
IPMI_LAN
UID
USB3/4(3.0)
P2-DIMMC2 P2-DIMMC1
P2-DIMMB1
P2-DIMMB2
P2-DIMMA1
P2-DIMMA2
CPU2_DMI
PCH_POR
T1
CPU2_POR
T1A
SXB2
VGA
SXB1C
CPU2_POR
T2A
CPU2_POR
T2C
SXB1A
P2-DIMMD2
P2-DIMMD1
P2-DIMME2
P2-DIMME1
P2-DIMMF1 P2-DIMMF2
USB2(3.0)
GPU PWR2
X11DPU-Z+
REV:1.01
JS1
JHFI2
JSD1
JSD2
S-SA
TA4
S-SA
TA5
NVME13
NVME12
JHFI1
JNVI2C1
NVME11
NVME10
JPW2
T-SGPIO3
FAN4
JRK1
JSDCARD1
JBT1
BT1
LEDM1
SXB1_3
LE2
JNVI2C2
GPU PWR1
JGPW4
JGPW2
JUSB3
FAN8
LED1
JUSBA1
SP1
JIPMB1
FAN1
FAN2
FAN3
FAN5
FAN6
FAN7
JPG1
JPME1
JF1
SXB1_2
SXB3_2
PSU1
JPW3
JPW1
JPW4
SXB3_3
SXB1_1
SXB3_1
JL1
JUIDB2
JTPM1
JS2
CPU2_POR
T3A
SXB1B
CPU2_POR
T3C
BMC
BIOS
PCH
PSU2
1. CPLD Header
2. BMC SMBus Header
1
2
BMC SMB (I
2
C) Header
A System Management Bus (SMBus) header for IPMI 2.0 is located at JIPMB1. Connect an
appropriate cable here to use the IPMB I
2
C connection on your system. Refer to the table
below for pin definitions.
External I
2
C Header
Pin Definitions
Pin#
Definition
1
Data
2
Ground
3
Clock
4
No Connection
