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X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual
10G SAN MAC
BIOS LICENSE
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DESIGNED IN USA
1G/10G MAC CODE
X10DRG-O+-CPU
REV: 1.00
IPMI CODE
BAR CODE
LD1
CLOSE 1st
OPEN 1st
CPU1
PCH
BMC
LAN
CTRL
LD2
JBT1
SW1
JITP1
J34
J33
JSPK1
JL1
JPB1
JPME2
JPL1
JVRM1
JPG1
JVRM2
J1
JPW22
JPW21
JPW24
JPW23
JPW17
JPW18
JPW14
JPW16
JPW15
JPW13
JPW3
JPW5
JPW7
JPW6
JPW12
JPW4
LE1
LE2
LEDM1
I-SGPIO1
I-SGPIO2
S-SGPIO
JTPM1
JF1
FA
N
4
FA
N
8
FA
N
3
FA
N
7
FA
N
2
FA
N
6
FA
N
5
FA
N
1
JSD2
JSD1
S-SA
TA
3
S-SA
TA
2
S-SA
TA
1
S-SA
TA
0
I-S
ATA
5
I-S
ATA
4
I-S
ATA
3
I-S
ATA
1
I-S
ATA
2
I-S
ATA
0
BT1
JPW10
JPP1
JPP2
J32
J31
CLOSE 1st
OPEN 1st
CPU2
USB7/8(3.0)
USB5/6(3.0)
USB4
P2 DIMMH3
P2 DIMMG3
P2 DIMME3
P2 DIMMF3
P1 DIMMC3
P1 DIMMD3
P1 DIMMA3
P1 DIMMB3
USB0/1
USB2/3
JWD1
JBR1
ON
RST
JF1
PWR
FAIL
LED
PS UID
2
NIC
1 LED
HDD
NIC
LED
PWR X
NMI
P1 DIMMC1
P2 DIMME1
COM1
P1 DIMMC2
P1 DIMMD1
P2 DIMME2
P1 DIMMD2
P2 DIMMF1
P2 DIMMF2
P1 DIMMB2
P2 DIMMH2
P1 DIMMB1
P1 DIMMA2
P2 DIMMH1
P1 DIMMA1
P2 DIMMG2
P2 DIMMG1
VGA
IPMI_LAN
LAN2 LAN1
1. Internal Speaker
(Buzzer)
2. TPM/80 Port
Internal Speaker
The internal speaker (SP1) provides
audible indications for various beep
codes. See the table on the right for
pin de
fi
nitions. Refer to the layout
below for the location of the internal
buzzer.
Internal Buzzer
Pin De
fi
nition
Pin# De
fi
nitions
Pin 1
Pos. (+)
Beep In
Pin 2
Neg. (-)
Alarm Speaker
TPM/Port 80 Header
A Trusted Platform Module/Port 80
header, located at JTPM1, provides
TPM support and Port 80 connection.
Use this header to enhance system
performance and data security. See
the table on the right for pin de
fi
nitions.
TPM/Port 80 Header
Pin De
fi
nitions
Pin# De
fi
nition
Pin# De
fi
nition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V (X)
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK4
14
SMB_DAT4
15
+3V_DUAL
16
SERIRQ
17
GND
18
CLKRUN# (X)
19
LPCPD#
20
LDRQ# (X)
1
2