Chapter 2: Installation
2-25
10G SAN MAC
BIOS LICENSE
+
1
1
+
DESIGNED IN USA
1G/10G MAC CODE
X10DRG-O+-CPU
REV: 1.00
IPMI CODE
BAR CODE
LD1
CLOSE 1st
OPEN 1st
CPU1
PCH
BMC
LAN
CTRL
LD2
JBT1
SW1
JITP1
J34
J33
JSPK1
JL1
JPB1
JPME2
JPL1
JVRM1
JPG1
JVRM2
J1
JPW22
JPW21
JPW24
JPW23
JPW17
JPW18
JPW14
JPW16
JPW15
JPW13
JPW3
JPW5
JPW7
JPW6
JPW12
JPW4
LE1
LE2
LEDM1
I-SGPIO1
I-SGPIO2
S-SGPIO
JTPM1
JF1
FA
N
4
FA
N
8
FA
N
3
FA
N
7
FA
N
2
FA
N
6
FA
N
5
FA
N
1
JSD2
JSD1
S-SA
TA
3
S-SA
TA
2
S-SA
TA
1
S-SA
TA
0
I-S
ATA
5
I-S
ATA
4
I-S
ATA
3
I-S
ATA
1
I-S
ATA
2
I-SA
TA
0
BT1
JPW10
JPP1
JPP2
J32
J31
CLOSE 1st
OPEN 1st
CPU2
USB7/8(3.0)
USB5/6(3.0)
USB4
P2 DIMMH3
P2 DIMMG3
P2 DIMME3
P2 DIMMF3
P1 DIMMC3
P1 DIMMD3
P1 DIMMA3
P1 DIMMB3
USB0/1
USB2/3
JWD1
JBR1
ON
RST
JF1
PWR
FAIL
LED
PS UID
2
NIC
1 LED
HDD
NIC
LED
PWR X
NMI
P1 DIMMC1
P2 DIMME1
COM1
P1 DIMMC2
P1 DIMMD1
P2 DIMME2
P1 DIMMD2
P2 DIMMF1
P2 DIMMF2
P1 DIMMB2
P2 DIMMH2
P1 DIMMB1
P1 DIMMA2
P2 DIMMH1
P1 DIMMA1
P2 DIMMG2
P2 DIMMG1
VGA
IPMI_LAN
LAN2 LAN1
Power Button
The Power Button connection is located on pins
1 and 2 of JF1. Momentarily contacting both pins
will power on/off the system. This button can also
be con
fi
gured to function as a suspend button
(with a setting in the BIOS - See Chapter 4). To
turn off the power when the system is in suspend
mode, press the button for 4 seconds or longer.
Refer to the table on the right for pin de
fi
nitions.
Power Button
Pin De
fi
nitions (JF1)
Pin# De
fi
nition
1
Signal
2
Ground
Reset Button
The Reset Button connection is located on pins
3 and 4 of JF1. Attach it to a hardware reset
switch on the computer case. Refer to the table
on the right for pin de
fi
nitions.
Reset Button
Pin De
fi
nitions (JF1)
Pin# De
fi
nition
3
Reset
4
Ground
1. Reset Button
2. PWR Button
Power Button
OH/Fan Fail LED
1
NIC1 Link LED
Reset Button
2
Power Fail LED
HDD LED
PWR LED
Reset
PWR
3.3V
ID_UID_SW/3/3V Stby
Ground
Ground
19
20
3.3V
X
Ground
NMI
X
NIC2 Link LED
NIC2 Activity LED
NIC1 Activity LED
UID LED
1
2
