13
Chapter 1: Introduction
Figure 1-4. Motherboard Layout
Below is a layout of the X11DPX-T with jumper, connector and LED locations shown. See
the table on the following page for descriptions. For detailed descriptions, pinout information
and jumper settings, refer to Chapter 4.
COM1
LAN
CTRL
DESIGNED IN USA
X11DPX-T
REV:1.01
I-SATA4~7 I-SATA0~3
FANC
FAND
CPU2
CPU1
BIOS
LICENSE
JBT1
M.2 CONNECTOR
SAN MAC
MAC CODE
JF1
BAR CODE
IPMI CODE
VGA
USB 2/3
BT1
JHFI1
JNVI2C2
JNVI2C1
PCH
FANA FAN2
FAN5
FAN1
P2-DIMMC1
P2-DIMMB1
P2-DIMMA1
P2-DIMMA2
P2-DIMMD2
P2-DIMMD1 P2-DIMME1
P2-DIMMF1
FAN6
P1-DIMMA2
P1-DIMMA1
P1-DIMMB1
P1-DIMMC1
JPWR1
JPWR2
JPWR3
JPI2C1
FAN4
LEDBMC
JSDCARD1
S-UM12
S-SATA0
S-SATA1
FANB
FAN3
JHFI2
JNCSI1
S-SGPIO
JSTBY1
JWD1
JSEN1
JVRM_SEL1
COM2
P1-DIMMF1
P1-DIMME1
P1-DIMMD1
P1-DIMMD2
SP1
USB 8 (3.0)
JTAG_HFI1
JTPM1
JPWR4
ALWAYS POPULATE DIMMx1 FIRST
ALWAYS POPULATE DIMMx1 FIRST
ALWAYS POPULATE DIMMx1 FIRST
ALWAYS POPULATE DIMMx1 FIRST
JUIDB1
(UID)
LED2
(UID-LED)
USB 6/7 (3.0)
JL1
LEDPWR
JSD1
JSD2
JIPMB1
JRK1
JPTG1
JP3
JPCIE1
1
(CPU2 SLOT1
1 PCI-E 3.0 x4 (IN x8))
JPME2
LAN 2
LAN 1 USB 0/1 IPMI_LAN
USB 4/5 (3.0)
BMC
JPCIE2
(CPU1 SLOT2 PCI-E 3.0 x16)
JPCIE1
(CPU1 SLOT1 PCI-E 3.0 x8)
JPCIE3
(CPU1 SLOT3 PCI-E 3.0 x8)
JPCIE6
(CPU2 SLOT6 PCI-E 3.0 x16)
JPCIE5
(CPU2 SLOT5 PCI-E 3.0 x8)
JPCIE7
(CPU1 SLOT7 PCI-E 3.0 x8)
JPCIE8
(CPU2 SLOT8 PCI-E 3.0 x16)
JPCIE4
(CPU1 SLOT4 PCI-E 3.0 x16)
JPCIE9
(CPU2 SLOT9 PCI-E 3.0 x8)
JPCIE10
(CPU2 SLOT10 PCI-E 3.0 x8)
1.5 Motherboard Layout
