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Chapter 4: Motherboard Connections
4.2 Headers and Connectors
Chassis Intrusion
A Chassis Intrusion header is located at JL1 on the motherboard. Attach the appropriate cable
from the chassis to inform you of a chassis intrusion when the chassis is opened. Refer to
the table below for pin definitions.
Chassis Intrusion
Pin Definitions
Pin#
Definition
1
Intrusion Input
2
Ground
1
9
2
10
JMD1: M.2-H PCIe 3.0 x4/SA
TA
3.0
JMD2_SRW1
JPG1
MH5
JLANLED3
JBM1
MH6
JLANLED2
JNVI2C1
JRK1
JIPMB1
JMD2_SRW2
JPME2
JWD1
JPH1
JPL3
JVRM1
JSDP4
JSDP1
JSFPLED1
JOPPS
JLANLED1
USB2/3
USB0/1
JSMB1
J1
JGP1
I-SA
TA3
I-SA
TA1
JSLIM2
JSLIM1
PCIe 3.0 X4
PCIe 3.0 X4
JNS1
FANB
MH2
JPT1
JRF1
JD1
JTPM1
JMD3_SRW1
JMD2
JSIM1
M.2_H PCIe 3.0 X2/S-SATA 3.0
MH4
JSTBY1
JSD1
FANA
FAN4
LED1
COM1
JF1
JMD3
M.2-H PCIe 3.0 X1
I-SGPIO1
CPU SLOT7 PCIe 4.0 X16
CPU SLOT6 PCIe 4.0 X8
JPCIE7
JPCIE6
LEDM1
JMD1_SRW1
VGA
LED2
LED3
JUIDB1
LAN3/4
JLAN2
LAN1/2
JLAN1
LAN5/6
SFP1
X12SDV-4C-SP6F
DESIGNED IN USA
REV: 1.02
CPU
MH3
USB4/5 (3.0)
IPMI_LAN
JPL2
JSDP3
JSDP2
JPL1
JPWR1
JPI2C1
FAN3
JL1
JBT1
JNVI2C2
FAN2
FAN1
MH1
JPV1
BT1
JPF1
DIMMA2 DIMMA1 DIMMB2 DIMMB1
LEDT2
LEDT4
LEDT1
LEDT3
COM Header
The motherboard has one COM header (COM1) that provides a serial connection .
COM Header (COM1)
Pin Definitions
Pin#
Definition
Pin#
Definition
1
DCD
2
DSR
3
RXD
4
RTS
5
TXD
6
CTS
7
DTR
8
RI
9
Ground
10
N/A
General Purpose I/O Header
The General Purpose Input/Output (GPIO) header at JPG1 is a general purpose I/O expander
on a pin header via the SMBus. Each pin can be configured to be an input pin or output pin
in 2.54mm pitch. The GPIO is controlled via the PCA9554APW 8-bit GPIO expansion from
PCH SMBus. The base address is 0xEFA0. The expander slave address is 0x70 for WRITE
and 0x71 for READ. See the table below for pin definitions.
General Purpose I/O Header
Pin Definitions
Pin#
Definition
Pin#
Definition
1
+3.3V Standby 2
GND
3
GP0
4
GP4
5
GP1
6
GP5
7
GP2
8
GP6
9
GP3
10
GP7