Supermicro SUPERSERVER 8048B-C0R3FT, User Manual

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SUPERSERVER 8048B-TR3F/C0R3FT User's Manual

Chipset Confi guration

North Bridge
This feature is used to con fi gure Intel North Bridge settings.

Integrated IO Confi guration
EV DFX (Device Function On-Hide) Features
When this feature is set to Enable, the EV_DFX Lock Bits that are located
inside a processor will always remain clear during electric tuning. The options
are
Disable
and Enable.

IIO0 Confi guration

CPU1 SLOT1 PCI-E 3.0 X16
Use the items below to con fi gure the PCI-E settings for a PCI-E port speci fi ed
by the user.
The following items will display:
•
PCI-E Port Link Status
•
PCI-E Port Link Max
•
PCI-E Port Link Speed
Link Speed
Use this item to select the PCI-E link speed for the PCI-E port speci fi ed by the
user. The options are Auto, GEN1 (2.5 GT/s),
GEN2 (5 GT/s)
, and GEN3 (8
GT/s).