Supermicro SUPERSERVER 6012P-i, User Manual

Page: 13 / 102

1-3
Chapter 1: Introduction
Figure 1-1. I/O Backplane
1-3 Mainboard Features
At the heart of the SuperServer 6012P-i lies the P4DPR-iG2, a dual Intel
Xeon processor motherboard designed to provide maximum performance.
Below are the main features of the P4DPR-iG2.
Chipset
The P4DPR-iG2 is based on Intel's E7500 ("Plumas") chipset, which is a
high-performance core logic chipset designed for dual-processor servers.
The E7500 chipset consists of four major components: the Memory Control-
ler Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0
(P64H2) and the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and
three for high-speed I/O communications. The MCH employs a 144-bit wide
memory bus for a DDR-200 (PC1600) memory interface, which provides a
total bandwidth of 3.2 GB/s. The ICH3 interface is a 266 MB/sec point-to-
point connection using an 8-bit wide, 66 MHz base clock at a 4x data
transfer rate. The P64H2 interface is a 1 GB/s point-to-point connection
using a 16-bit wide, 66 MHz base clock at a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including
a two-channel UDMA100 bus master IDE controller, USB host controllers, an
integrated LAN controller, a System Management Bus controller and an
AC'97 compliant interface.
The P64H2 PCI-X Hub provides a 16-bit connection to the MCH for high-
performance IO capability and the 64-bit PCI-X interface.
Ethernet Ports USB Ports
Mouse Port Keyboard Port
COM1 Port
Low Profile PCI Slot Standard PCI Slot
VGA Port