Supermicro SBI-7126T-T1E, User Manual

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6-7
Chapter 6: BIOS
CPU Bridge Configuration
The menu options in the N
ORTH
B
RIDGE
C
ONFIGURATION
submenu and their descriptions
are shown in Table 6-6 .
NorthBridge Configuration
The menu options in the N
ORTH
B
RIDGE
C
ONFIGURATION
submenu and their descriptions
are shown in Table 6-7 .
Table 6-6. CPU Bridge Configuration Submenu
Menu Option Description
CPU Information
(Static)
Displays for CPU Revision, Current QPI Frequency, Current Memory Frequency,
Memory Reference Code Revision and CSI Reference Code Revision are all
statically displayed at the top of this menu.
QPI Links Speed
This setting allows you to transition the QPI links to Full-speed or leave them in
Slow-mode.
QPI Frequency
This setting allows you to transition the links to the specified speed when
transitioning the links to full-speed (if supported by all components). Options
include
Auto , 4.800GT, 5.866GT and 6.400GT.
QPI L0s and L1 This setting allows you to Enable or Disable QPI L0s and L1.
Memory Frequency
This setting forces a DDR3 frequency slower than the common tCK detected via
SPD. Options include
Auto , Force DDR-800, Force DDR-1066 and Force
DDR-1333.
Memory Mode
This setting sets the Memory Mode. Options include Independent (independent
channel), Channel Mirroring (mirrors channel space between channels),
Lockstep (locksteps channel 0 and 1) and Sparing (for sparing mode).
Demand Scrubbing This setting Enables or Disables ECC demand scrubbing.
Patrol Scrubbing This setting Enables or Disables ECC patrol scrubbing.
NUMA Support This setting Enables or Disables NUMA support.
Serial Debug
Message Level Use this setting to specify what level of debug messages to display. Options
include
None , Min, Max and Test.
Table 6-7. NorthBridge Configuration Submenu
Menu Option Description
Static Infomation
This menu displays static information for NB Revision and the Current QPI
Frequency.
Crystal Beach / DMA
This setting allows you to Disable or Enable the Crystal Beach DMA
Configuration.