PXIe-700 User Guide
Page 5
Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email:
© Sundance Digital Signal Processing Inc 2016.
4
Factory use
5
Factory use
6
Not used
Table 3 - Switch (SW1)
Pins 1 and 2 are connected to Flash address pins and are used to select the configuration bit-
stream start address. A total of 4 bitstream can be stored and used for FPGA configuration. Pins
3 to 5 should always be set to OFF, ON, OFF as set by the factory. This board only uses Master
BPI x16 mode as it has 16-bit Fast parallel NOR Flash connected to the FPGA.
2.9 Clocks
This board requires several clocks for FPGA and high-speed serial transceivers. There are 6
clock sources available:
1) Clock provided by the PCIe Interface
2) 66.6 MHz FPGA_EMC clock for FPGA configuration from Flash
3) A Voltage-Controlled Crystal Oscillator providing a tunable 125MHz clock via
CDCM61004 for:
a. GTXs
b. FPGA Logic
4) A second VCXO with independent control voltage for use in White Rabbit extreme-
precision clock distribution protocol
5) MMCX connectors to provide external clock for user application
6) External Ref Clock for Transceivers via MMCX connectors
A low jitter clock generator from TI CDCM61004 is used to provide 3 clocks for FPGA logic and
GTX’s.
http://www.ti.com/lit/ds/symlink/cdcm61004.pdf
The output frequencies can range from 43.75 MHz to 683.264 MHz see table 4 of CDCM61004
data sheet. The output frequency divider can be chosen using control pins. On PXIe-700 a 25
MHz clock input clock is used and for the output the control pins are set using 0 ohm resistors
R187
– R193. The factory default settings for output clock is 125 MHz by populating R191,
R192.
For any other clock output please contact Sundance DSP Inc.
Note: Please see appendix for pinouts
2.10 JTAG
A 14-pin 2mm pitch pin header is provided for connection to a Xilinx USB Programmer (using
the standard ribbon cable). This allows access to the internals of the FPGA for configuration and
debugging.
2.11 PXIe
The board conforms to PXIe specifications and provides a hybrid connector for PCIe and control
signals.
