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Sundance Spas PXIe-700, User Manual

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PXIe-700 User Guide

 

Page 15 

Rev. 1.7 

Sundance Digital Signal Processing Inc.

 

4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. 

Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: 

[email protected]

 

www.sundancedsp.com

    © Sundance Digital Signal Processing Inc 2016. 

4.1.3  SFP+ 

Note: The control signals are connected to 1.8v bank 

 

PXIe 700 SFP+ Pinout 

S.No 

SFP+ Pin 

FPGA Pin 

1 

 

P2 

2 

SFP_TX- 

P1 

3 

 

T6 

4 

SFP_RX- 

T5 

5 

SFP_TX_FAULT 

AH16 

6 

SFP_TX_DISABLE 

AJ16 

7 

SFP_MOD_DETECT 

AE16 

8 

SFP_RS0 

Y18 

9 

SFP_RS1 

Y19 

10 

SFP_LOS 

AF16 

Table 8 - SFP+ Pinout 

4.1.4  MMCX 

PXIe 700 MMCX Pinout 

Connector 

Pin_name 

FPGA 

Pin 

P1 

MGTX 

N8 

P2 

MGTX_REFCLK- 

N7 

P3 

FPGA 

U28 

P4 

FPGA_REFCLK- 

U27 

P5 

MGTX 

N4 

P6 

MGTX_AUX_TX- 

N3 

P7 

MGTX 

R4 

P8 

MGTX_AUX_RX- 

R3 

Table 9 - MMCX Pinout 

Summary of Contents for PXIe-700

Page 1: ...ains proprietary information of Sundance DSP Inc The document is delivered on condition that it is used exclusively to evaluate the technical contents and pricing therein it shall not be disclosed dup...

Page 2: ...ion Comments Originator Date 1 0 Initial Release Stephen Malchi Aug 25th 2016 1 1 Added VADJ details Stephen Malchi Sep 18th 2016 1 2 Updated Flash features and errors Stephen Malchi Sep 30th 2016 1 3...

Page 3: ...agram and Pictures 2 2 2 BPI FLASH Memory 3 2 3 Xilinx FPGA 3 2 4 Memory 3 2 5 GTX High Speed Transceivers 3 2 6 HPC FMC 4 2 7 LEDs 4 2 8 Switches 4 2 9 Clocks 5 2 10 JTAG 5 2 11 PXIe 5 3 Operation 7...

Page 4: ...ures Figure 1 PXIe 700 Block Diagram 2 Figure 2 PXIe 700 frontal image 2 Figure 3 JTAG Configuration 9 Table of Tables Table 1 High Speed Transceivers 4 Table 2 LEDs 4 Table 3 Switch SW1 5 Table 4 VAD...

Page 5: ...interface It fully complies with PXIe standard 1 1 Hardware features The hardware has the following features 1 Kintex 7 FPGA XC7K325T 1FFG900C or XC7K410T 1FFG900C optional faster speed grades 2 4 la...

Page 6: ...ck Diagram and Pictures The following diagram shows the major blocks of PXIe 700 Front Panel Xilinx Kintex 7 FPGA XC7K325T 1FFG900C or XC7K410T 1FFG900C JTAG J3 Gen2 x4 4LEDs PCIe clock Rear End Conne...

Page 7: ...and out of the module Various interfaces are available to the FPGA from which data is fed for processing after which the processed data can be passed to the outside world via any of the interfaces The...

Page 8: ...fferential clocks pins connected to the FPGA As mentioned in section 2 5 10 high speed serial links from the FPGA are available on this connector Note Please see appendix for pinout 2 7 LEDs There are...

Page 9: ...a GTXs b FPGA Logic 4 A second VCXO with independent control voltage for use in White Rabbit extreme precision clock distribution protocol 5 MMCX connectors to provide external clock for user applica...

Page 10: ...5 827 3103 Fax 1 775 827 3664 email sales sundancedsp com www sundancedsp com Sundance Digital Signal Processing Inc 2016 J2 973028 from ERNI backplane connector This is used to provide PCIe signals i...

Page 11: ...ost provides 3 3 volt and 12 volt input power These voltages are brought to the board through the backplane connector The module generates the following voltages 1 1 0v 16A 0 9v for 1C VCCINT VCCBRAM...

Page 12: ...ote Rev 3 0 PCB On power up VADJ voltage comes up as 1 8v If a FMC module with VADJ 2 5v or 3 3v is populated then the module will receive 1 8v till the FPGA is configured with the right VADJ_SEL pins...

Page 13: ...Xilinx JTAG emulator connected to a PC with Vivado 2016 2 Start Vivado and Open hardware manager and connect to the local target The FPGA device is detected by the software Select the device and prog...

Page 14: ...r BPI mode Note Set pins 3 to 5 on switch SW1 to OFF ON OFF for the FPGA to boot from flash Multiple bitstreams can be stored in the flash by setting the Warm Boot Start Address WBSTAR register availa...

Page 15: ...on Sundance Scom Sundance Communication library along with a default FPGA bitstream which will provide users a multi channel DMA interface to talk to the user application The default package is not s...

Page 16: ...e LVDS signals PIN A FPGA_PIN Rev 3 0 FPGA_PIN Rev 4 0 B FPGA_PIN Rev 3 0 FPGA_PIN Rev 4 0 C 1 PXIe_CLK AD18 AD18 PXIe_CLK AE18 AE18 GND 2 PRSNT PWREN GND 3 SMBDAT M29 M29 SMBCLK M28 M28 GND 4 MPWRGD...

Page 17: ...Y5 GND 7 1PETP4 1PETN4 GND 8 1PERP4 1PERN4 GND 9 1PETP7 1PETN7 GND 10 1PERP7 1PERN7 GND Table 5 PXIe 700 J2 Pinout J3 214443 from ERNI backplane connector This is used to provide PXI control signals N...

Page 18: ...igital Signal Processing Inc 4790 Caughlin Parkway 233 Reno NV 89519 0907 U S A Tel 1 775 827 3103 Fax 1 775 827 3664 email sales sundancedsp com www sundancedsp com Sundance Digital Signal Processing...

Page 19: ...ol signals are connected to 1 8v bank PXIe 700 SFP Pinout S No SFP Pin FPGA Pin 1 SFP_TX P2 2 SFP_TX P1 3 SFP_RX T6 4 SFP_RX T5 5 SFP_TX_FAULT AH16 6 SFP_TX_DISABLE AJ16 7 SFP_MOD_DETECT AE16 8 SFP_RS...

Page 20: ...Table 10 LEDs Pinout 4 1 6 Clocks Note Pins are connected to 2 5v bank PXIe 700 Clock Pinout S No Pin_name FPGA Pin Clock Frequency 1 FPGA_EMCCLK R24 66 MHz 2 FPGA_VCXO_CLK L25 20 MHz 3 MGT_SYS_CLK0...

Page 21: ...E5 RAS AD9 DQ14 AF5 CAS AE9 DQ15 AF6 WE AE11 DQ16 AJ4 CS AF11 DQ17 AH6 RESET AD12 DQ18 AH5 CKE AD11 DQ19 AH2 ODT AG10 DQ20 AJ2 DM0 AD4 DQ21 AJ1 DM1 AF3 DQ22 AK1 DM2 AH4 DQ23 AJ3 DM3 AF8 DQ24 AF7 DQS0...

Page 22: ...4 DQ9 Y30 A12 Y23 DQ10 AA30 BA0 AD24 DQ11 AB29 BA1 AC24 DQ12 AB30 BA2 AD22 DQ13 AD27 RAS AD21 DQ14 AD28 CAS AE21 DQ15 AB27 WE AE23 DQ16 AH29 CS AF23 DQ17 AE28 RESET AD23 DQ18 AF28 CKE AE24 DQ19 AE30 O...

Page 23: ...ax 1 775 827 3664 email sales sundancedsp com www sundancedsp com Sundance Digital Signal Processing Inc 2016 4 1 8 J5 Header Note Pins are connected to 2 5v bank J5 Header Pinout Pin No Signal FPGA P...

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