Sun Microsystems Ultra 5, Service Manual

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C-1
A P P E N D I X
C
Functional Description
This appendix provides a functional description of the Ultra 5 system.
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Section C.1 “System” on page C-1
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Section C.2 “Clocking” on page C-27
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Section C.3 “Address Mapping” on page C-29
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Section C.4 “Interrupts” on page C-31
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Section C.5 “Power” on page C-35
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Section C.6 “Motherboard” on page C-36
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Section C.7 “Jumper Descriptions” on page C-37
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Section C.8 “Enclosure” on page C-40
C.1 System
The Ultra 5 system is an UltraSPARC port architecture (UPA)-based uniprocessor
machine that uses peripheral component interconnect (PCI) as the I/O bus. The CPU
module, APB ASIC (advanced PCI bridge), and UPA graphics communicate with
each other using the UPA64S and PCI protocols. The RISC ASIC routes interrupts to
the CPU module.
This section discusses the following topics:
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Section C.1.1 “CPU Module” on page C-3
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Section C.1.2 “PCI-IDE Interface” on page C-4
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Section C.1.3 “Memory Architecture” on page C-10
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Section C.1.4 “PCI Riser Board” on page C-15
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Section C.1.5 “ASICs” on page C-19
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Section C.1.6 “EBus2 Devices” on page C-21
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Section C.1.7 “Power and Standby Switching” on page C-26
The following figure shows a functional block diagram of the system unit.