Sun Microsystems Ultra 5, Service Manual

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C-10 Sun Ultra 5 Service Manual • February 2000
FIGURE C-8
PCI-Based Graphics Functional Block Diagram (PGX24)
C.1.3 Memory Architecture
The memory architecture uses the 168-pin JEDEC standard extended data out (EDO)
3.3-VDC buffered DIMMs. The memory controller unit (MCU) is embedded within
the CPU module. All memory addressing and control are driven from the CPU
module to the motherboard and then buffered before being gated to the DIMM
DRAMs (assuming buffered DIMMs). The data path on the DRAM side is 144 bits
(2-bit x 72-bit) wide, and data is multiplexed to 72 bits wide on the processor side by
using the transceiver switches.
The interface between the CPU module MCU and the system memory subsystem
consists of the following:
■
A 12-bit multiplexed row-column address
■
Two column address select (CAS) lines
■
Eight row address select (RAS) lines
■
One write enable (WE) line
■
Support for 60-ns EDO DRAMs
Up to four DIMMs can be installed. Having only four DIMM connectors requires a
stacked and dual-bank DIMM architecture to achieve the 1-Gbyte capacity.
All memory transfers have error checking code (ECC). The MCU performs ECC
generation and checking. The following figure is a functional block diagram of the
memory interface.
DB15
4-Mbyte
SGRAM EMI
filters
PCI-B Bus
PGX24 graphics
controller
(ATI 3D Rage Pro)