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SR/AI
SR/AP
Hardware Reference
Release r09
Page 54 of 76
7 Application Diagram
The following schematic shows a typical application of SR. The module is connected to
some MCU running the application layer. MCU and SR use the same 3,3V power
supply. Provisions are made for upgrading the firmware (BOOT0 and EXT-RES# are managed by
the MCU). The serial interface has RTS/CTS flow control but no UICP support in this example. The
Hangup feature to close down the link is provided. As an option to save power, there is an external
slow clock oscillator. All other module pins may be left unconnected.
Host MCU
VDD
GND
+3V3
GPIO (o)
In this example SR is connected to an MCU supporting RTS/CTS flow control and Hangup.
Firmware update is supported (BOOT0, EXT-RES# connected).
The slow clock oscillator (32,768kHz ) is optional; it helps to save power during power down states.
1k
SR/AI
C-1,E-6,F-6
VSUP
GND
B-1 EXT-RES#
BOOT0
GPIO (o)
UART-RXD
UART-TXD
UART-CTS#
UART-RTS#
GPIO[4]/Hangup
TXD (o)
RXD (i)
RTS# (o)
CTS# (i)
GPIO (o)
SLCK
32,768kHz
square
+3V3
The oscillator is optional. Leave A-6 open
or tie to GND if the oscillator is not present.
E-1
D-2
F-4
F-3
D-7
D-4
A-6
all GND pads (14) must be connected.
Blocking capacitors not shown.
pushpull or OD
pushpull
pushpull
Figure 20: Typical Application Schematics
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