STMicroelectronics STP1612PW05 Manual Download Page 24 | Manualshive

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Time-out alert of GCLK disconnection

STP1612PW05

24/35

Doc ID 15819 Rev 4

15

Time-out alert of GCLK disconnection

When the PWCLK signal is disconnected for around 1 second, all output ports will be turned
off automatically. This function will protect the LED display system from staying ON
indefinitely and prevent excessive current from damaging the power system. The default is
set to ‘enable” when bit “0” is 0. When the PWCLK is active again and new serial data are
moved in, the driver resumes to work after resetting the internal counters and comparators.

Figure 14.

Time-out alert application scheme

PWCLK

500K

STP1612PW05

STP1612PW05

STP1612PW05

STP1612PW05

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Summary of Contents for STP1612PW05

Page 1: ...maximum output current value for all the 16 channels is set by a single resistor from 3 mA to 60 mA The device features 8 bit gain 256 steps for global LED brightness adjustment with two selectable ra...

Page 2: ...ical characteristics 9 5 Timing waveform 13 6 Principle of operation 14 7 Definition of configuration register 16 8 Grey scales data loading 17 9 Setting the PWM gray scale counter 18 9 1 PWM data syn...

Page 3: ...STP1612PW05 Contents Doc ID 15819 Rev 4 3 35 16 Package mechanical data 25 17 Revision history 34...

Page 4: ...nd SYNC control Serial interface UVLO POR VDD GND SDI CLK LE SDO Constant current output channels 1 16 TSD 16 bit Configuration Register Shift register dual size mode 16 or 256 bit PWCLK Dual range ga...

Page 5: ...cy at 5 V Output voltage Current accuracy Output current VDD temp Between bits Between ICs 1 0 1 5 6 15 to 60 5 V 25 C 0 2 1 5 6 3 to 15 Table 3 Typical current accuracy at 3 3 V Output voltage Curren...

Page 6: ...1 OUT10 OUT9 OUT5 OUT14 OUT15 PWCLK GND Table 4 Pin description Pin n Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal used to shift data on r...

Page 7: ...Value Unit VDD Supply voltage 0 to 7 V VO Output voltage 0 5 to 20 V IO Output current 60 mA VI Input voltage 0 4 to VDD V IGND GND terminal current 1300 mA fCLK Clock frequency 50 MHz TJ Junction tem...

Page 8: ...ERIAL OUT 1 mA IOL Output current SERIAL OUT 1 mA VIH Input voltage 0 7 VDD VDD V VIL Input voltage GND 0 3 VDD V twLAT LE pulse width VDD 3 3 V to 5 0 V 20 ns twCLK CLK pulse width 10 ns twEN PWCLK p...

Page 9: ...A VOL Output voltage SDO IOL 1 0 mA TA 40 125 C 0 4 V VOH IOH 1 0 mA TA 40 125 C VDD 0 4 V dIOUT1 Current skew Channel IOUT 10 mA VO 1 0 V Rext 69 k 1 5 3 0 dIOUT2 Current skew IC IOUT 10 mA VO 1 0 V...

Page 10: ...age SDO IOL 1 0 mA TA 40 125 C 0 4 V VOH IOH 1 0 mA TA 40 125 C 2 9 V dIOUT1 Current skew channel IOUT 10 5 mA VO 1 0 V Rext 69 k at 10 mA 1 5 3 0 dIOUT2 Current skew IC IOUT 10 8 mA VO 1 0 V Rext 69...

Page 11: ...D1 PWCLK OUTn4 1 1 Refer to the timing waveform where n 0 1 2 3 100 ns tPD2 LE SDO 2 2 In timing of read configuration and read error status code the next CLK rising edge should be tPD2 after the fall...

Page 12: ...OUTn4 1 1 Refer to the timing waveform Figure 4 where n 0 1 2 3 120 ns tPD2 LE SDO 2 2 In timing of read configuration and read error status code the next CLK rising edge should be tPD2 after the fal...

Page 13: ...STP1612PW05 Timing waveform Doc ID 15819 Rev 4 13 35 5 Timing waveform Figure 5 Timing waveform PWCLK PWCLK PWCLK...

Page 14: ...l latch High 2 or 3 Buffer data are transferred to the comparators Read configuration High 4 or 5 Move out configuration register to the shift register Enable error detection High 6 or 7 Detect the st...

Page 15: ...iple of operation Doc ID 15819 Rev 4 15 35 Figure 6 Timing diagram ATA ATCH LOBAL ATCH 2EAD ONFIGURATION 7RITE ONFIGURATION 3 3 0REVIOUS ATA EXT ATA 3 3 3 0REVIOUS ATA EXT ATA 3 3 0REVIOUS ATA 3 3 0RE...

Page 16: ...00 64 times of MSB 1 6 bit PWM counting plus once of LSB 1 6 bit PWM counting 1 Please refer to setting the PWM counting mode section 01 16 times of MSB 6 bit PWM counting by 1 4 PWCLK plus once of L...

Page 17: ...h methods the first incoming data packet is relative to the output 15 the following packet is relative to the output 14 and so on up to the output 0 If F 0 when a data packet has been loaded the latch...

Page 18: ...lgorithms that support e PWM technology scrambled PWM With e PWM the total PWM cycles can be broken down into MSB most significant bits and LSB least significant bits of gray scale cycles and the MSB...

Page 19: ...he new data are loaded with a global latch the device wait until all the PWM counter completes the counting cycle before updating them with the new data at the next CLK rising edge Conversely if bit A...

Page 20: ...ort circuit error detection a channel must be on the command enable error detection starts the detection After 0 5 s typ the command read error status code allows to get the status from the serial out...

Page 21: ...et by the bit9 bit2 of the configuration register The default value of G is 1 For your information the output current is about 20 mA when Rext 34 70 k and 10 mA when Rext 69 6 k if G is set to default...

Page 22: ...1 Bit 9 is HC bit The setting is in the low current range when HC 0 and in the high current range when HC 1 2 Bit 8 to bit 2 are DA6 DA0 The relationship between these bits and current gain G is HC 1...

Page 23: ...ious one E g OUT4n has no delay OUTn4 1 has 40ns delay OUTn4 2 has 80ns delay OUTn4 3 has 120 ns delay 14 Thermal protection Thermal flag provides an indication about the status of the junction temper...

Page 24: ...function will protect the LED display system from staying ON indefinitely and prevent excessive current from damaging the power system The default is set to enable when bit 0 is 0 When the PWCLK is ac...

Page 25: ...e ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Table 16 TSSOP24 mechanical data Dim mm inch Min Typ Max Min Typ Max A 1 1 0 043 A1...

Page 26: ...24 tape and reel Dim mm inch Min Typ Max Min Typ Max A 330 12 992 C 12 8 13 2 0 504 0 519 D 20 2 0 795 N 60 2 362 T 22 4 0 882 Ao 6 8 7 0 268 0 276 Bo 8 2 8 4 0 323 0 331 Ko 1 7 1 9 0 067 0 075 Po 3 9...

Page 27: ...Dim mm inch Min Typ Max Min Typ Max A 2 65 0 104 a1 0 1 0 2 0 004 0 008 a2 2 45 0 096 b 0 35 0 49 0 014 0 019 b1 0 23 0 32 0 009 0 012 C 0 5 0 020 c1 45 typ D 15 20 15 60 0 598 0 614 E 10 00 10 65 0 3...

Page 28: ...Package mechanical data STP1612PW05 28 35 Doc ID 15819 Rev 4 Figure 17 SO 24 package dimensions...

Page 29: ...tape and reel Dim mm inch Min Typ Max Min Typ Max A 330 12 992 C 12 8 13 2 0 504 0 519 D 20 2 0 795 N 60 2 362 T 30 4 1 197 Ao 10 8 11 0 0 425 0 433 Bo 15 7 15 9 0 618 0 626 Ko 2 9 3 1 0 114 0 122 Po...

Page 30: ...04 0 006 A2 0 8 1 1 05 0 031 0 039 0 041 b 0 19 0 30 0 007 0 012 c 0 09 0 20 0 004 0 0089 D 7 7 7 8 7 9 0 303 0 307 0 311 D1 4 7 5 0 5 3 0 185 0 197 0 209 E 6 2 6 4 6 6 0 244 0 252 0 260 E1 4 3 4 4 4...

Page 31: ...4 31 35 Table 21 QFN24 4x4 mechanical data Dim mm mils Min Typ Max Min Typ Max A 1 00 39 4 A1 0 00 0 05 0 0 2 0 b 0 18 0 30 7 1 11 8 D 3 9 4 1 153 5 161 4 D2 2 6 2 8 76 8 88 6 E 3 9 4 1 153 5 161 4 E2...

Page 32: ...Package mechanical data STP1612PW05 32 35 Doc ID 15819 Rev 4 Figure 20 QFN24 4x4 mechanical drawing...

Page 33: ...15819 Rev 4 33 35 DIM mm inch MIN TYP MAX MIN TYP MAX A 330 12 992 C 12 8 13 2 0 504 0 519 D 20 2 0 795 N 99 101 3 898 3 976 T 14 4 0 567 Ao 4 35 0 171 Bo 4 35 0 171 Ko 1 1 0 043 Po 4 0 157 P 8 0 315...

Page 34: ...Document revision history Date Revision Changes 17 Jun 2009 1 Initial release 10 Aug 2009 2 Updated Section 9 2 on page 19 and Table 12 on page 14 29 Oct 2009 3 Updated Figure 2 on page 6 and Table 21...

Page 35: ...WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UN...

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