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STM32L100RC

ODD bit value, digital contribution leads to a min of (I2SDIV/(2*ODD) and a max of
(ODD)/(2*ODD). Fs max is supported for each mode/condition.

Figure 21. I

S slave timing diagram (Philips protocol)

(1)

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LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 22. I

S master timing diagram (Philips protocol)

(1)

Guaranteed by characterization results, not tested in production.

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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Summary of Contents for STM32L100RC

Page 1: ...for RTC with calibration High Speed Internal 16 MHz Internal low power 37 kHz RC Internal multispeed low power 65 kHz to 4 2 MHz PLL for CPU clock and USB 48 MHz Pre programmed bootloader USB and USA...

Page 2: ...modes 19 3 4 Clock management 20 3 5 Low power real time clock and backup registers 22 3 6 GPIOs general purpose inputs outputs 22 3 7 Memories 23 3 8 DMA direct memory access 23 3 9 LCD liquid crysta...

Page 3: ...6 1 Parameter conditions 40 6 1 1 Minimum and maximum values 40 6 1 2 Typical values 40 6 1 3 Typical curves 40 6 1 4 Loading capacitor 40 6 1 5 Pin input voltage 40 6 1 6 Power supply scheme 41 6 1 7...

Page 4: ...s 77 6 3 16 Communications interfaces 78 6 3 17 12 bit ADC characteristics 86 6 3 18 DAC electrical specifications 91 6 3 19 Operational amplifier characteristics 93 6 3 20 Comparator 95 6 3 21 LCD co...

Page 5: ...urrent consumption in Low power sleep mode 53 Table 21 Typical and maximum current consumptions in Stop mode 54 Table 22 Typical and maximum current consumptions in Standby mode 56 Table 23 Peripheral...

Page 6: ...e 56 Maximum source impedance RAIN max 90 Table 57 DAC characteristics 91 Table 58 Operational amplifier characteristics 93 Table 59 Comparator 1 characteristics 95 Table 60 Comparator 2 characteristi...

Page 7: ...veforms and measurement circuit 79 Figure 17 SPI timing diagram slave mode and CPHA 0 81 Figure 18 SPI timing diagram slave mode and CPHA 1 1 81 Figure 19 SPI timing diagram master mode 1 82 Figure 20...

Page 8: ...handheld equipment Application control and user interface PC peripherals gaming GPS and sport equipment Alarm systems wired and wireless sensors video intercom Utility metering This STM32L100RC datas...

Page 9: ...s Moreover the STM32L100RC device contains standard and advanced communication interfaces up to two I2Cs three SPIs two I2S three USARTs and an USB It also includes a real time clock and a set of back...

Page 10: ...128 bit DAC USB crystal less and many others will clearly allow you to build very cost optimized applications by reducing BOM Table 1 Ultra low power STM32L100RC device features and peripheral counts...

Page 11: ...ed peripherals STM8L15xxx STM32L15xxx and STM32L162xx share identical peripherals which ensure a very easy migration from one family to another Analog peripherals ADC DAC and comparators Digital perip...

Page 12: ...7 0 56 ELWV ELW 63 6 6 VWHP 6XSSO PRQLWRULQJ 9 9 9 9 6XSSO PRQLWRULQJ 3 2 3257 3 2 3257 3 PD 0 3 PD 0 3 ORFN 0JPW 57 B287 3 3 7 6 706 6 7 7 2 DV 352 5 0 7 227 9 9 25 9UHI 0 38 3 0 FKDQQHOV 3 0 FKDQQHO...

Page 13: ...AM or Flash memory and internal regulator in low power mode to minimize the regulator s operating current In low power run mode the clock frequency and the number of enabled peripherals are both limit...

Page 14: ...nt RTC timestamp event or RTC Wakeup event occurs Standby mode without RTC Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entir...

Page 15: ...oltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz 1ws 32 kHz to 16 MHz 0ws Range 1 8 MHz to 16 MHz 1ws 32 kHz to 8 MHz 0ws Range 2 2 1MHz to 4 2 MHz 1ws 32 kHz to 2 1 M...

Page 16: ...Y Y Y Y Y Y DMA Y Y Y Y Programmable Voltage Detector PVD Y Y Y Y Y Y Y Power On Reset POR Y Y Y Y Y Y Y Power Down Rest PDR Y Y Y Y Y Y High Speed Internal HSI Y Y High Speed External HSE Y Y Low Spe...

Page 17: ...t and 32 bit Timers Y Y Y Y IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y Touch sensing Y Y Systic Timer Y Y Y Y GPIOs Y Y Y Y Y Y 3 pins Wakeup time to Run mode 0 s 0 4 s 3 s 46 s 8 s 58 s Consumption VDD 1 8 to...

Page 18: ...imal interrupt latency 3 3 Reset and supply management 3 3 1 Power supply schemes VDD 1 65 to 3 6 V external power supply for I Os and the internal regulator Provided externally through VDD pins VSSA...

Page 19: ...pt can be generated when VDD VDDA drops below the VPVD threshold and or when VDD VDDA is higher than the VPVD threshold The interrupt service routine can then generate a warning message and or put the...

Page 20: ...n to a 0 5 accuracy Auxiliary clock source two ultra low power clock sources that can be used to drive the LCD controller and the real time clock 32 768 kHz low speed external crystal LSE 37 kHz low s...

Page 21: ...ENT OR NOT 3 TEMPO CK PLL PRESCALER 0 0 CK USB 6CO 6CO MUST BE AT Z 4 393 05 072 53 4 4 0 0 USBEN AND NOT DEEPSLEEP TIMER EN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPS...

Page 22: ...interrupt To prevent false tamper event like ESD event these three tamper inputs can be digitally filtered 3 6 GPIOs general purpose inputs outputs Each of the GPIO pins can be configured by software...

Page 23: ...A is able to manage memory to memory peripheral to memory and memory to peripheral transfers The DMA controller supports circular buffer management avoiding the generation of interrupts when the contr...

Page 24: ...e allows high priority conversions to be done by interrupting a scan mode which runs in as a background task The ADC includes a specific low power mode The converter is able to operate at maximum spee...

Page 25: ...and reference voltage The STM32L100RC device embeds two comparators sharing the same current bias and reference voltage The reference voltage can be internal or external coming from an I O One compara...

Page 26: ...Any of the general purpose timers can be used to generate PWM outputs TIM2 TIM3 TIM4 all have independent DMA request generation These timers are capable of handling quadrature incremental encoder sig...

Page 27: ...ardware or software configurable through the option bytes The counter can be frozen in debug mode 3 14 5 Window watchdog WWDG The window watchdog is based on a 7 bit downcounter that can be set as fre...

Page 28: ...terface It has software configurable endpoint setting and supports suspend resume The dedicated 48 MHz clock is generated from the internal main PLL the clock source must use a HSE crystal oscillator...

Page 29: ...cell The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L100RC device th...

Page 30: ...l pin name Pin type S Supply pin I Input only pin I O Input output pin I O structure FT 5 V tolerant I O TC Standard 3 3 V I O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull...

Page 31: ...C_TAMP1 RTC_TS RTC_OUT 3 PC14 OSC32_IN 3 I O PC14 OSC32_IN 4 PC15 OSC32_OUT 3 I O PC15 OSC32_OUT 5 PH0 OSC_IN 4 I PH0 OSC_IN 6 PH1 OSC_OUT 4 O PH1 OSC_OUT 7 NRST I O NRST 8 PC0 I O FT PC0 LCD_SEG18 AD...

Page 32: ...CD_SEG5 ADC_IN8 COMP1_INP OPAMP2_VOUT VREF_OUT 27 PB1 I O FT PB1 TIM3_CH4 LCD_SEG6 ADC_IN9 COMP1_INP VREF_OUT 28 PB2 I O FT PB2 BOOT1 BOOT1 COMP1_INP 29 PB10 I O FT PB10 TIM2_CH3 I2C2_SCL USART3_TX LC...

Page 33: ...P 46 PA13 I O FT JTMS SWDIO JTMS SWDIO 47 VSS_2 S VSS_2 48 VDD_2 S VDD_2 49 PA14 I O FT JTCK SWCLK JTCK SWCLK 50 PA15 I O FT JTDI TIM2_CH1_ETR SPI1_NSS SPI3_NSS I2S3_WS LCD_SEG17 JTDI 51 PC10 I O FT P...

Page 34: ...scillator pins OSC32_IN OSC32_OUT can be used as general purpose PH0 PH1 I Os respectively when the LSE oscillator is off after reset the LSE oscillator is off The LSE has priority over the GPIO funct...

Page 35: ...ART2_RTS SEG0 TIMx_IC2 EVENT OUT PA2 TIM2_CH3 TIM9_CH1 USART2_TX SEG1 TIMx_IC3 EVENT OUT PA3 TIM2_CH4 TIM9_CH2 USART2_RX SEG2 TIMx_IC4 EVENT OUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK TIMx_IC1 EVENT...

Page 36: ...T PB5 TIM3_CH2 I2C1_ SMBA SPI1_MOSI SPI3_MOSI I2S3_SD SEG9 EVENT OUT PB6 TIM4_CH1 I2C1_SCL USART1_TX EVENT OUT PB7 TIM4_CH2 I2C1_SDA USART1_RX EVENT OUT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL SEG16 EVENT OUT...

Page 37: ...OUT PC3 SEG21 TIMx_IC4 EVENT OUT PC4 SEG22 TIMx_IC1 EVENT OUT PC5 SEG23 TIMx_IC2 EVENT OUT PC6 TIM3_CH1 I2S2_MCK SEG24 TIMx_IC3 EVENT OUT PC7 TIM3_CH2 I2S3_MCK SEG25 TIMx_IC4 EVENT OUT PC8 TIM3_CH3 SE...

Page 38: ...T OUT PC14 OSC32_IN TIMx_IC3 EVENT OUT PC15 OSC32_OUT TIMx_IC4 EVENT OUT PD2 TIM3_ETR COM7 SEG31 SEG43 TIMx_IC3 EVENT OUT PH0OSC_IN PH1OSC_OUT Table 8 Alternate function input output continued Port na...

Page 39: ...UW 203 5 0 RUWH 0 QWHUQDO 3HULSKHUDOV 3HULSKHUDOV 65 0 1RQ YRODWLOH PHPRU UHVHUYHG UHVHUYHG UHVHUYHG 6 VWHP PHPRU 2SWLRQ E WH DWD 3520 UHVHUYHG ODVK PHPRU OLDVHG WR ODVK RU V VWHP PHPRU GHSHQGLQJ RQ 2...

Page 40: ...s or minus three times the standard deviation mean 3 6 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C VDD 3 6 V for the 1 65 V VDD 3 6 V voltage range They are given o...

Page 41: ...heme 06 9 QDORJ 26 3 203 9 3 2V 287 1 HUQHO ORJLF 38 LJLWDO 0HPRULHV 6WDQGE SRZHU FLUFXLWU 6 57 DNH XS ORJLF 57 EDFNXS UHJLVWHUV 1 Q 5HJXODWRU 966 9 95 95 966 HYHO VKLIWHU 2 RJLF 9 Q 95 Q 9 1 QXPEHU R...

Page 42: ...open 2 Option 2 LCD power supply is provided by the internal step up converter VSEL switch is closed an external capacitance is needed for correct behavior of this converter 6 1 8 Current consumption...

Page 43: ...Max Unit IVDD Total current into sum of all VDD_x power lines source 1 100 mA IVSS 2 Total current out of sum of all VSS_x ground lines sink 1 100 IVDD PIN Maximum current into each VDD_x power pin s...

Page 44: ...PCLK1 Internal APB1 clock frequency 0 32 fPCLK2 Internal APB2 clock frequency 0 32 VDD Standard operating voltage BOR detector disabled 1 65 3 6 V BOR detector enabled at power on 1 8 3 6 BOR detector...

Page 45: ...nge as long as TJ does not exceed TJ max see Table 63 Thermal characteristics on page 100 Table 13 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit t...

Page 46: ...44 2 48 Rising edge 2 47 2 54 2 58 VPVD4 PVD threshold 4 Falling edge 2 57 2 64 2 69 Rising edge 2 68 2 74 2 79 VPVD5 PVD threshold 5 Falling edge 2 77 2 83 2 88 Rising edge 2 87 2 94 2 99 VPVD6 PVD t...

Page 47: ...REF values 5 mV TCoeff 3 Temperature coefficient 40 C TJ 110 C 20 50 ppm C 0 C TJ 50 C 20 ACoeff 3 Long term stability 1000 hours T 25 C 1000 ppm VDDCoeff 3 Voltage coefficient 3 0 V VDDA 3 6 V 2000 p...

Page 48: ...conditions summarized in Table 12 General operating conditions unless otherwise specified The MCU is placed under the following conditions All I O pins are configured in analog input mode All periphe...

Page 49: ...V VOS 1 0 10 4 MHz 0 915 1 1 mA 8 MHz 1 75 2 1 16 MHz 3 4 3 9 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 2 1 2 8 16 MHz 4 2 4 9 32 MHz 8 25 9 4 HSI clock source 16 MHz Range 2 VCORE 1 5 V VOS 1 0 10 16 MHz...

Page 50: ...5 V VOS 1 0 10 4 MHz 0 755 1 4 mA 8 MHz 1 5 2 1 16 MHz 3 3 5 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 1 8 2 8 16 MHz 3 6 4 1 32 MHz 7 15 8 3 HSI clock source 16 MHz Range 2 VCORE 1 5 V VOS 1 0 10 16 MHz...

Page 51: ...Hz 33 99 MSI clock 4 2 MHz 4 2 MHz 145 210 Supply current in Sleep mode Flash ON fHSE fHCLK up to 16 MHz included fHSE fHCLK 2 above 16 MHz PLL ON 2 Range 3 VCORE 1 2 V VOS 1 0 11 1 MHz 60 5 130 2 MHz...

Page 52: ...1 kHz fHCLK 131 kHz TA 40 C to 25 C 26 29 TA 55 C 28 31 TA 85 C 36 42 TA 105 C 52 64 All peripherals OFF code executed from Flash VDD from 1 65 V to 3 6 V MSI clock 65 kHz fHCLK 32 kHz TA 40 C to 25 C...

Page 53: ...clock 131 kHz fHCLK 131 kHz Flash ON TA 40 C to 25 C 17 19 TA 55 C 18 21 TA 85 C 22 25 TA 105 C 30 35 TIM9 and USART1 enabled Flash ON VDD from 1 65 V to 3 6 V MSI clock 65 kHz fHCLK 32 kHz TA 40 C t...

Page 54: ...ty 2 TA 40 C to 25 C 1 55 6 TA 55 C 2 15 7 TA 85 C 3 55 12 TA 105 C 6 3 27 LCD ON 1 8 duty 3 TA 40 C to 25 C 3 9 10 TA 55 C 4 65 11 TA 85 C 6 25 16 TA 105 C 9 1 44 RTC clocked by LSE external quartz 3...

Page 55: ...ed 2 LCD enabled with external VLCD static duty division ratio 256 all pixels active no LCD connected 3 LCD enabled with external VLCD 1 8 duty 1 3 bias division ratio 64 all pixels active no LCD conn...

Page 56: ...og TA 40 C to 25 C VDD 1 8 V 0 905 A TA 40 C to 25 C 1 15 1 9 TA 55 C 1 5 2 2 TA 85 C 1 75 4 TA 105 C 2 1 8 3 2 RTC clocked by LSE external quartz no independent watchdog 3 TA 40 C to 25 C VDD 1 8 V 0...

Page 57: ...8 9 7 0 8 9 A MHz fHCLK TIM3 11 2 9 0 7 1 9 0 TIM4 12 9 10 4 8 2 10 4 TIM5 14 4 11 5 9 0 11 5 TIM6 4 0 3 1 2 4 3 1 TIM7 3 8 3 0 2 3 3 0 LCD 5 8 4 6 3 6 4 6 WWDG 2 9 2 3 1 8 2 3 SPI2 6 5 5 2 4 1 5 2 S...

Page 58: ...mode 2 Fast mode 5 IDD PVD BOR 6 2 6 IDD IWDG 0 25 1 Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled in the following conditions fHCLK 32 M...

Page 59: ...onversion of VDD 2 DAC is in buffered mode output is left floating 6 Including supply current of internal reference voltage Table 24 Low power mode wakeup timings Symbol Parameter Conditions Typ Max 1...

Page 60: ...k source AC timing diagram Table 25 High speed external user clock characteristics 1 1 Guaranteed by design not tested in production Symbol Parameter Conditions Min Typ Max Unit fHSE_ext User external...

Page 61: ...n the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonat...

Page 62: ...equivalent serial resistance of the crystal RS 3 RS 30 20 pF IHSE HSE driving current VDD 3 3 V VIN VSS with 30 pF load 3 mA IDD HSE HSE oscillator power consumption C 20 pF fOSC 16 MHz 2 5 startup 0...

Page 63: ...Guaranteed by characterization results not tested in production Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency 32 768 kHz RF Feedback resistor 1 2 M C 2 2 R...

Page 64: ...F Caution To avoid exceeding the maximum value of CL1 and CL2 15 pF it is strongly recommended to use a resonator with a load capacitance CL 7 pF Never use a resonator with a load capacitance of 12 5...

Page 65: ...tested in production Accuracy of the factory calibrated HSI oscillator VDDA 3 0 V TA 25 C 1 3 3 Guaranteed by test in production 1 3 VDDA 3 0 V TA 0 to 55 C 1 5 1 5 VDDA 3 0 V TA 10 to 70 C 2 2 VDDA...

Page 66: ...error after factory calibration 0 5 DTEMP MSI 1 MSI oscillator frequency drift 0 C TA 105 C 3 DVOLT MSI 1 MSI oscillator frequency drift 1 65 V VDD 3 6 V TA 25 C 2 5 V IDD MSI 2 MSI oscillator power...

Page 67: ...ge range 3 3 fOVER MSI MSI oscillator frequency overshoot Any range to range 5 4 MHz Any range to range 6 6 1 This is a deviation for an individual part once the initial frequency has been measured 2...

Page 68: ...iate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT 2 24 MHz PLL input clock duty cycle 45 55 fPLL_OUT PLL output clock 2 32 MHz tLOCK PLL lock t...

Page 69: ...n 1 5 2 5 mA Table 35 Flash memory and data EEPROM endurance and retention Symbol Parameter Conditions Value Unit Min 1 1 Guaranteed by characterization results not tested in production Typ Max NCYC 2...

Page 70: ...tion are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and th...

Page 71: ...itive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n...

Page 72: ...ressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is in...

Page 73: ...ut leakage current 4 VSS VIN VDD I Os with LCD 50 nA VSS VIN VDD I Os with analog switches 50 VSS VIN VDD I Os with analog switches and LCD 50 VSS VIN VDD I Os with USB 250 VSS VIN VDD TC and FT I Os...

Page 74: ...s summarized in Table 12 All I Os are CMOS and TTL compliant Table 42 Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL 1 2 1 The IIO current sunk by the device must always r...

Page 75: ...O out Output rise and fall time CL 50 pF VDD 2 7 V to 3 6 V 125 ns CL 50 pF VDD 1 65 V to 2 7 V 250 10 Fmax IO out Maximum frequency 3 CL 50 pF VDD 2 7 V to 3 6 V 10 MHz CL 50 pF VDD 1 65 V to 2 7 V 2...

Page 76: ...Parameter Conditions Min Typ Max Unit VIL NRST 1 NRST input low level voltage 0 3 VDD V VIH NRST 1 NRST input high level voltage 0 39VDD 0 59 VOL NRST 1 NRST output low level voltage IOL 2 mA 2 7 V VD...

Page 77: ...input capture external clock PWM output DL E 670 538 1567 9 LOWHU QWHUQDO UHVHW WHUQDO UHVHW FLUFXLW Table 45 TIMx 1 characteristics 1 TIMx is used as a general term to refer to the TIM2 TIM3 and TIM4...

Page 78: ...must be at least 4 MHz to achieve fast mode I C frequencies It must be a multiple of 10 MHz to reach the 400 kHz maximum I C fast mode clock Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 s...

Page 79: ...V 1 2 1 RP External pull up resistance fSCL I2C speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges the tolerance on the achieved speed is 2 These vari...

Page 80: ...tHCLK ns th NSS NSS hold time Slave mode 2tHCLK tw SCKH 2 tw SCKL 2 SCK high and low time Master mode tSCK 2 5 tSCK 2 3 tsu MI 2 Data input setup time Master mode 5 tsu SI 2 Slave mode 6 th MI 2 Data...

Page 81: ...nts are done at CMOS levels 0 3VDD and 0 7VDD DL F W DK EWhd D K KhdW hd W D K hd D E d Khd E Khd WK WK d E E h E E K K K K DL 6 QSXW 3 026 1387 0 62 287 387 3 06 2 87 06 1 7 287 6 1 6 287 32 32 7 1 W...

Page 82: ...diagram master mode 1 1 Measurement points are done at CMOS levels 0 3VDD and 0 7VDD AI 6 3 UTPUT 0 3 54054 3 054 0 3 3 54 4 3 54 3 0 0 4 54 33 INPUT TC 3 TW 3 TW 3 TR 3 TF 3 TH IGH 3 UTPUT 0 0 0 0 T...

Page 83: ...characterization results not tested in production Differential input sensitivity I USB_DP USB_DM 0 2 V VCM 2 Differential common mode range Includes VDI range 0 8 2 5 VSE 2 Single ended receiver thre...

Page 84: ...Master data 32 bits 64xFs MHz Slave data 32 bits 64xFs DCK I2S clock frequency duty cycle Slave receiver 48KHz 30 70 tr CK I2S clock rise time Capacitive load CL 30pF 8 ns tf CK I2S clock fall time 8...

Page 85: ...ram Philips protocol 1 1 Guaranteed by characterization results not tested in production 2 LSB transmit receive of the previously transmitted byte No LSB transmit receive is sent before the first byte...

Page 86: ...Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1 8 3 6 V VREF Positive reference voltage 1 8 1 VDDA VREF Negative reference voltage VSSA IVDDA Current on the VDDA input pin 1000 1450...

Page 87: ...fADC tSTAB Power up time 3 5 s 1 The Vref input can be grounded if neither the ADC nor the DAC are used this allows to shut down an external voltage reference 2 The current consumption through VREF is...

Page 88: ...VDDA 3 6 V 1 8 V VREF 2 4 V fADC 4 MHz RAIN 50 TA 40 to 105 C 4 6 5 LSB EO Offset error 2 4 EG Gain error 4 6 ED Differential linearity error 1 2 EL Integral linearity error 1 5 3 ET Total unadjusted...

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Page 90: ...6V1 Table 56 Maximum source impedance RAIN max 1 Ts s RAIN max k Ts cycles fADC 16 MHz 2 Multiplexed channels Direct channels 2 4 V VDDA 3 6 V 1 8 V VDDA 2 4 V 2 4 V VDDA 3 6 V 1 8 V VDDA 2 4 V 0 25 N...

Page 91: ...load worst code 0xF1C 320 520 RL 2 Resistive load DAC output buffer ON 5 k CL 2 Capacitive load 50 pF RO Output impedance DAC output buffer OFF 12 16 20 k VDAC_OUT Voltage on DAC_OUT output DAC outpu...

Page 92: ...No RL CL 50 pF DAC output buffer OFF 8 12 tSETTLING Settling time full scale for a 12 bit code transition between the lowest and the highest input codes till DAC_OUT reaches final value 1LSB CL 50 pF...

Page 93: ...d from code 0x000 and 0xFFF when buffer is OFF and from code giving 0 2 V and VDDA 0 2 V when buffer is ON 8 In buffered mode the output can overshoot above the final value for low input code starting...

Page 94: ...n voltage Normal mode ILOAD max or RL min VDD 100 mV Low power mode VDD 50 VOLSAT Low saturation voltage Normal mode 100 Low power mode 50 m Phase margin 60 GM Gain margin 12 dB tOFFTRIM Offset trim t...

Page 95: ...00 h ICOMP1 Current consumption 3 3 Comparator consumption only Internal reference voltage not included 160 260 nA Table 60 Comparator 2 characteristics Symbol Parameter Conditions Min Typ Max 1 1 Gua...

Page 96: ...4 3 12 VLCD5 LCD internal reference voltage 5 3 26 VLCD6 LCD internal reference voltage 6 3 4 VLCD7 LCD internal reference voltage 7 3 55 Cext VLCD external capacitance 0 1 2 F ILCD 1 1 LCD enabled wi...

Page 97: ...liance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 7 1 LQFP64 10 x 10 mm 64 pin low profile quad flat package information Figure...

Page 98: ...0 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 11 800 12 000 12 200 0 4646 0 4724 0 4803 D1 9 800 10 00...

Page 99: ...yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these...

Page 100: ...PINT max is the product of IDD and VDD expressed in Watts This is the maximum chip internal power PI O max represents the maximum power dissipation on output pins where PI O max VOL IOL VDD VOH IOH t...

Page 101: ...7 2 1 Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org 06Y 9 7HPSHUDWXUH 3 P RUELGGHQ DUHD 7 7 PD 4...

Page 102: ...information scheme Example STM32 L 100 R C T 6 TR Device family STM32 ARM based 32 bit microcontroller Product type L Low power Device subfamily 100 Device with LCD Pin count R 64 pins Flash memory si...

Page 103: ...cription 12 Sept 2014 3 Updated communication interfaces section including I2S characteristics Updated DMIPS features in cover page and description section Updated Table 7 STM32L100RC pin definitions...

Page 104: ...e choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right i...

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