DocID018909 Rev 11
799/1731
RM0090
Real-time clock (RTC)
828
Negative calibration can be performed with a resolution of about 2 ppm while positive
calibration can be performed with a resolution of about 4 ppm. The maximum calibration
ranges from
−
63 ppm to 126 ppm.
The calibration can be performed either on the LSE or on the HSE clock.
Caution:
Digital calibration may not work correctly if PREDIV_A < 6.
Case of RTCCLK=32.768 kHz and P1=128
The following description assumes that ck_apre frequency is 256 Hz obtained with an LSE
clock nominal frequency of 32.768 kHz, and PREDIV_A set to 127 (default value).
The ck_spre clock frequency is only modified during the first 2xDC minutes of the 64-minute
cycle. For example, when DC equals 1, only the first 2 minutes are modified. This means
that the first 2xDC minutes of each 64-minute cycle have, once per minute, one second
either shortened by 256 or lengthened by 128 RTCCLK cycles, given that each ck_apre
cycle represents 128 RTCCLK cycles (with P1=128).
Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125829120 RTCCLK cycles (64min x 60 s/min x 32768 cycles/s). This is
equivalent to +4.069 ppm or-2.035 ppm per calibration step. As a result, the calibration
resolution is +10.5 or
−
5.27 seconds per month, and the total calibration ranges from +5.45
to
−
2.72 minutes per month.
In order to measure the clock deviation, a 512 Hz clock is output for calibration.Refer to
Section 26.3.14: Calibration clock output
.
26.3.11
RTC smooth digital calibration
RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range
from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series
of small adjustments (adding and/or subtracting individual RTCCLK pulses). These
adjustments are fairly well distributed so that the RTC is well calibrated even when observed
over short durations of time.
The smooth digital calibration is performed during a cycle of about 2
20
RTCCLK pulses, or
32 seconds when the input frequency is 32768 Hz.
This cycle is maintained by a 20-bit
counter, cal_cnt[19:0], clocked by RTCCLK.
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles
to be masked during the 32-second cycle:
•
Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-
second cycle.
•
Setting CALM[1] to 1 causes two additional cycles to be masked
•
Setting CALM[2] to 1 causes four additional cycles to be masked
•
and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.
Note:
CALM[8:0] (RTC_CALRx) specifies the number of RTCCLK pulses to be masked during the
32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked
during the 32-second cycle
at the moment when cal_cnt[19:0] is 0x80000
; CALM[1]=1
causes two other cycles to be masked
(when cal_cnt is 0x40000 and 0xC0000)
; CALM[2]=1
causes four other cycles to be masked
(cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000)
;
and so on up to CALM[8]=1 which causes 256 clocks to be masked
(cal_cnt = 0xXX800)
.
