General-purpose timers (TIM2 to TIM5)
RM0090
616/1731
DocID018909 Rev 11
As in the previous example, you can initialize both counters before starting counting.
shows the behavior with the same configuration as in
but in trigger
mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
Figure 178. Triggering timer 2 with Enable of timer 1
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of
Timer 2 with the enable of Timer 1. Refer to
for connections. To ensure the
counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer 2):
•
Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the
TIM1_CR2 register).
•
Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM1_SMCR register).
•
Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).
•
Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).
•
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
•
Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note:
In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.
TIMER 2-TIF
Write TIF=0
75
00
01
CK_INT
TIMER1-CEN=CNT_EN
TIMER1-CNT
TIMER2-CNT
02
TIMER1-CNT_INIT
CD
00
E7
E8
EA
TIMER2-CNT_INIT
TIMER2
write CNT
E9
