BS_Serial memory interface
RM0082
302/844
Doc ID 018672 Rev 1
When a read request occurs in normal mode (that is, frequency up to 20 MHz), the SMI
sends the following data sequence to the bank selected by the AHB address bits [24.25].
●
Read data bytes instruction opcode (8’h03)
●
3- or 2-byte address (depending on the ADD_LENGTH bit of SMI_CR1 register,
) from the MSB to the LSB,
●
Then, clock is sent to the memory until the end of burst requested by the AHB master.
In contrast, when a read request occurs in fast mode (that is, frequency ranging from 20
MHz to 50 MHz), the following sequence is sent:
●
Read data bytes at high speed instruction opcode (8’h0B),
●
3- or 2-byte address (depending on the ADD_LENGTH bit of SMI_CR1 register,
) from the MSB to the LSB,
●
1 dummy byte (8’h00),
●
Then, clock is sent to the memory until the end of burst requested by the AHB master.
The external memory bank remains selected as long as
●
There is no external memory address jump,
●
No new commands are sent to the SMI (such as write enable request, read status
register command set, software mode or write burst mode, write request, bank disable,
prescaler configuration change),
●
No memory access error occurs.
Note:
The memory bank also remains selected when the address rolls over from 0x00FF_FFFF to
0x0000.0000 within the same bank.
15.5.2 Write
request
A write request from AHB master to external SPI memory is served only if SMI is in
Hardware mode, otherwise an error flag is set (ERF1 flag in the SMI_SR register,
). Wrapping bursts are not allowed as long as external SPI memories don’t
support them, and an ERROR response is sent back to the AHB master.
When a write request occurs, this request is forwarded to external memory only if both
following conditions are fulfilled:
●
At first, selected bank is in Write mode (corresponding bit in WM field of SMI_SR
register is flagged). Otherwise, a dedicated error flag is set (the ERF2 flag in the
SMI_SR register) and an ERROR response is sent back to the AHB master.
Note:
To enable write mode, select the memory bank using the BS bits in the SMI_CR2 register
(
), and then set the WEN bit in the SMI_CR1 register (
●
Then, no write in progress. The WIP bit of external memory status register in the
SMI_SR register (bit [0]) must be cleared (see
). If this condition is not
met, AHB is stalled until WIP = 1‘b0.
When the 2 conditions above are met, the following data sequence is sent to the bank
selected by AHB address bits [24-25]:
●
Page program instruction opcode (8’h02,
●
3- or 2-byte address (depending on the ADD_LENGTH bit of SMI_CR1 register,
) from the MSB to the LSB,
●
Then, all data bytes (from bit 7 to bit 0) are transferred, starting with address given in
previous step and incrementing it to the last depending on the size of the Write request.
