RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
119/844
should also be so large to hold enough words to consume data for a single write transaction
related to the bus. The data may actually be written into the buffers from the bus at a later
time, depending on the priority of the request and the number of transactions in the
Command Queue.
10.4.4
DRAM command processing
The DRAM command processing logic is used to process the commands in the Command
Queue.
The logic organizes the commands to the memory devices in such a way that data
throughput is maximized. Bank opening and closing cycles are used for data transfers.
The logic uses a variety of factors to determine when to issue bank open and close
commands. The logic reviews the entire Command Queue to look-ahead which banks are to
be accessed in the future. The timing is then set to meet the trc and tras_min timing
parameters of the memory devices, values which were programmed into the Memory
Controller on initialization. This flexibility allows the Memory Controller to be tuned to extract
the maximum performance out of memory devices. The parameters that relate to DRAM
device protocol are listed in Chapter “Register Interface”.
10.4.5 Latency
By using the placement logic of the command queue in the Memory Controller core, a new
request by any port can be immediately placed at the top of the command queue or can
interrupt an ongoing request. This scheme allows a high priority request to be processed in
the shortest possible time.
However, since there are many factors that determine the placement into the command
queue, there are also many factors that affect the actual latency of the command. These
factors include:
The coherency status of the transactions already in the command queue: If there is a data
coherency conflict with a transaction already in the command queue, the new transaction
will be placed after the transaction that produced the conflict. The position of the conflicting
transaction determines the latency of the high priority READ or WRITE command.
●
The priority status of the transactions already in the command queue: If the new
command has a higher priority than those already in the command queue, the new
request will be serviced ahead of the lower priority command. As a result, the latency of
the new command will be lower than the latency of the older command.
●
The READ, WRITE, and bank information of the transactions already in the command
queue: In general, READs will be placed ahead of WRITEs when both are of the same
priority level. READ commands are grouped with other READ commands of similar
priorities and WRITE commands are grouped with other WRITE commands of similar
priorities. Among these groupings, transactions with similar bank and different row
destinations are separated as much as possible.
If every placement conditions are met, a new command would be placed at the top of the
command queue. However, if the new command is of a higher priority than the transaction
executing, the current command will be interrupted and the new command will be processed
first. The interruption will occur at a natural burst boundary of the DRAMs. The interrupted
transaction will be placed at the top of the placement queue and it will be recovered after the
new request is completed. The page status of the new transaction determines when the
current transaction is interrupted.
