DDR memory controller (MPMC)
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10
DDR memory controller (MPMC)
10.1 Overview
SPEAr300 integrates a high performances multi-port memory controller able to support
DDR-Mobile and DDR2 double data rate memory devices. The multi-port architecture
ensures memory is shared efficiently among different high-bandwidth client modules.
It offers 6 internal ports. One of them is reserved to registers access during the controller
initialization while the other five are used to access the external memory.
It also include the physical layer (PHY) and some DLL that allows a fine tuning of all the
timing parameter to maximize the data valid windows at every frequency in the allowed
range.
Figure 7.
MPMC block diagram
10.2 Signal
description
The following
describe the signals either for the internal connections
that the external ones.
AHB-CFG
AHB0
AHB1
AHB2
AHB3
AHB4
PHY
Ext.Memory I/F
Multi port Memory Controller
CORE
Controller
Table 53.
External memory Interface signals
Signal name
Direction
Description
DDR_CLK_P
Out
Differential memory clock. Positive line
DDR_CLK_N
Out
Differential memory clock. Negative line.
DDR_DQS_(1:0)
Bidir
Differential memory data strobe positive line. Drove during
write transaction and received from memory device during
read transfer.
