4.5
Status model
4 – 23
4.5
Status model
The SR124 status registers follow the hierarchical IEEE–488.2 format.
status registers
A block diagram of the status register array is given in Figure 4.1.
7
X
5
4
3
2
1
0
undefined
MSS: Master Summary Status
ESB: Event Status Bit
undefined
undefined
undefined
undefined
undefined
7
6
5
4
3
2
1
0
Status Byte
SB
SRE
5
4
3
2
0
5
4
3
2
0
OPC: Operation c omplete
undef
DDE: Device error
EXE: Execution error
CME: Command error
undef
undef
QYE: Query error
ESR
ESE
Standard Event Status
Figure 4.1: Status Model for the SR124 Analog Lock-In Amplifier
There are three categories of registers in the status model of the lock-
in:
Event Registers : These read-only registers record the occurrence of defined
events within the lock-in. If the event occurs, the correspond-
ing bit is set to 1. Upon querying an event register, any set bits
within it are cleared. These are sometimes known as “sticky
bits,” since once set, a bit can only be cleared by reading its
value. Event register names end with
SR
or
EV
.
Enable Registers : These read
/
write registers define a bitwise mask for their cor-
responding event register. If any bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set in
the Status Byte. Enable register names end with
SE
or
EN
.
Status Byte : This read-only register represents the top of the status model,
and is populated with summary bit messages and interface
condition bits. Enabled bits within the Status Byte generate the
remote Request Service event.
At power-on, all status registers are cleared.
4.5.1
Status byte (SB)
The Status Byte is the top-level summary of the SR124 status model.
When enabled by the Service Request Enable register, a bit set in the
Status Byte causes the MSS (Master Summary Status) bit to be set.
SR124
Analog Lock-In Amplifier
