4 – 2
Circuitry
4.1
Circuit Discussion
4.1.1
Input amplifier and protection circuitry
The front-end amplifier Q101 is a matched JFET pair biased with
5.5 mA per side. Closed-loop feedback is provided by U105 for an
overall first-stage gain of 10.
The JFET inputs are protected by TVS101. A pair of bootstrapped
diodes, D101 and D102, isolate the amplifier from this device. Series
input resistors R103 and R104 (100
Ω
each) provide some passive
input protection as well, and limit the input current when TVS101
turns on. For excessive input overvoltages, one or both of these
resistors may be damaged or destroyed.
4.1.2
Programmable gain stages
To preserve pulse shapes while changing amplifier gain, a “fixed-
gains with attenuators” topology was chosen for the SIM910. Low
impedance precision divider ladders (R201
−
R204, and R207
−
R211)
provide programmable gain steps without introducing excessive
noise at lower gains. Gain allocations are noted on the schematic,
indicating which switches within U201 and U203 are closed based
on gain.
The overall gain of the SIM910 is trimmed at U204, the gain of which
is adjustable by
±
10 %. The final output stage rolls the gain o
ff
slowly
above 1 MHz, and includes a high-current output bu
ff
er (U207) ca-
pable of driving long coaxial cables and other reactive loads. Note
that the 50
Ω
output resistor R225 is common to both the front- and
rear-panel output connectors. Because of this, at most one of the
outputs may be terminated with an external 50
Ω
load.
4.1.3
Digital control
The SIM910 is controlled by microcontroller U405. Amplifier config-
uration is set by shift registers U301 and U302, while the front panel
LED indicators are driven directly by processor port pins. U406 is a
serial EEPROM providing non-volatile memory for amplifier config-
urations.
A critical aspect of the design is the clock-stop circuitry implemented
by U403 and U404. A simple RC-oscillator is enabled or disabled at
pin 1 of U403, which is driven by synchronizing flip-flop U403B to
ensure that no “runt” clock pulses are produced that would violate
U405’s minimum clock periods. Four separate clock-starting signals
are combined by U402:
•
Power-on reset
SIM910
JFET Preamp
