Obsolete Product(s) - Obsolete Product(s)
STMicroelectronics Confidential
55/62
AN1290 I²C Control Section
9
I²C Control Section
9.1
I²C Bus Reminder
Since I²C bus documentation is widespread today, a short reminder will be enough.
I²C bus consists of two wires, SCL (clock) and SDA (data), plus ground. The logic is positive. Both
SCL and SDA have a pull-up resistor to 5V, and all connected ports are open-collector or open-
drain, i.e. act as wired AND (line is LOW if at least one port is LOW).
The ICs connected to the bus either belong to the MASTER or the SLAVE category:
●
MASTERS control the clock and send/receive data
●
SLAVES receive or send data when required by a MASTER, but do not control the clock.
All data is exchanged as 8-bit bytes (MSB first, LSB last), followed by an Acknowledge bit if a
SLAVE is the receiver. A logic 1 is recognized each time SDA remains HIGH for a full SCL pulse, a
logic 0 each time SDA remains LOW for a full SCL pulse. If a MASTER switches SDA to LOW while
SCL is HIGH this is interpreted as START. The opposite transition is interpreted as STOP. A SLAVE
receiver will acknowledge receipt of the data by maintaining SDA LOW for the full duration of the
next clock pulse, while the MASTER transmitter leaves SDA floating.
9.2
TDA9112 Family as I²C Bus Device
For a complete overview of I²C programming values, refer to
Section 10: I²C Bus Control Register
In the TDA9112 family, all settings are programmed through the I²C bus. All ICs in the family are
software-compatible, including the TDA9112A which uses more instructions. Clock frequency may
be as high as 400 kHz. The duration of any pulse must be higher than 50ns, because parasitic
spikes are filtered with this time constant. The input threshold for receiving data on pins 31 (SDA)
and 30 (SCL) is 2.2 V typ when the supply on pin 32 is 5 V. Logic levels are TTL compatible when
sending data.
The logic section is biased by an internal 5 V supply. At start-up, all internal registers stay reset to
their default value until the supply voltage exceeds 8.5 V, they are reset again when it goes lower
than 6.5 V (8.0 V and 6.8 V for TDA 9112A).
The TDA9112 family is SLAVE only. Like all I²C devices it has an 8 bit-address which is
(hexadecimal) 8C when receiving and 8D when sending data (the TDA9115 does not send data).
To know the affectation of the various registers, please refer to the register map.
9.3
Receiving Data
The data for the various controls are stored in 24
⋅
(8-bit registers) with their 24 sub addresses on 8
bits (31 registers for the TDA9112A). Since not more than the 5 or 6 LSB are necessary to define 24
or 31 sub addresses, the 3 or 2 MSB are undefined.
Nevertheless, for the sake of compatibility with future software it is recommended to set them to 0.
The same applies to all unspecified bits.
When the microprocessor sends one piece of data to one register, the following sequence will
appear on the bus: (Codes sent by the TDA9112 in Bold)
(Start)(8C)(ackn)(subadress)(ackn)(data)(ackn)(Stop)
