AN2339
Clock management
9/20
Figure 5.
32.768 kHz oscillator
3.3 USB
clock
STR91x contains a USB 2.0 Full Speed device module interface that operates at a precise
frequency of 48 MHz. This clock is usually provided by an external oscillator connected to
the USB clock pin USB_CLK48M. However, to save board space and cost, the 48 MHz USB
clock can also be generated by the internal PLL using one single external oscillator for both
system and USB module.
Note:
Care is required when programming the PLL multiplier and divider factors, not to exceed the
maximum allowed operating frequency (96 MHz). At power up, the CPU defaults to run the
oscillator clock, as the PLL is not ready (locked). The LOCK bit is set when the PLL clock
has stabilized.
3.4 TIM
clock
Like the USB interface, TIM0/TIM1 and TIM2/TIM3 can receive an external clock on pin
EXTCLK_T0T1 and EXTCLK_T2T3 respectively.
3.5 Output
clock
The STR91xF devices can optionally output a 25 MHz clock to the external Ethernet PHY
interface device via output pin MII_PHYCLK, in this case, the STR91xF must use a 25 MHz
signal on its main oscillator input. The advantage here is that an inexpensive 25 MHz crystal
may be used to source a clock to both STR91xF and the external PHY device. Alternatively
an external 25 MHz oscillator can be connected directly to the external PHY interface
device. In this case the STR91xF can use a crystal at a frequency other than 25 MHz.
X1_RTC
STR91xF
X2_RTC
32 kHz c
ryst
al
For more details concerning capacitance, refer to the crystal manufacturer datasheet.
V
CC1
V
CC1
can be:
V
DDQ
: if you don’t want to preserve tamper function when V
DD
and V
DDQ
are switched off
V
BATT
: if you want to preserve tamper function when V
DD
and V
DDQ
are switched off.
TAMPER_IN