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ST STNRG011A User Manual Download Page 6

3.2

Faults parameters

3.2.1

Surge detection

Size:1 bit
Enable / disable the surge comparator.
Available values are:
•

Disabled

•

Enabled

The surge comparator is connected to the VAC pin and its threshold is 430 V.

3.2.2

PFC OC2 detection

Size:1 bit
Enables / disables the PFC OC2 comparator.
Available values are:
•

Disabled

•

Enabled

The PFC OC2 comparator is connected to the PFC_CS pin and its threshold is 900 mV.

3.2.3

Max number of PFC OC2

Size:2 bits
Sets the number of consecutive PFC OC2 events before shutting down.
Available values are:
•

1

•

2

•

4

•

8

Use

The suggested value is “2”, since it is a good compromise between the noise rejection and protection
reactiveness.
The value “1” can be used if minimum intervention time is required: in this case, pay attention because some
noise could trigger the protection. Higher values can be used in case of noisy boards (in this case, the reaction to
real OCP2 events will be slower).

3.2.4

PFC HW OVP detection

Size: 1 bit
Enable / disable the hardware PFC OVP comparator.
Available values are:
•

Disabled

•

Enabled

The PFC OVP comparator is the hardware protection against the bulk overvoltage. It is connected to the PFC_FB
pin and its threshold is set at 2.3 V.
The fault is always immediate and shuts down the system.

Use

It is suggested to leave the PFC OVP comparator enabled.

3.2.5

LLC OC2 detection

Size: 1 bit
Enables / disables the LLC OC2 comparator.
Available values are:
•

Disabled

UM3002

Faults parameters

UM3002

-

Rev 1

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Summary of Contents for STNRG011A

Page 1: ...enerator and a sophisticated digital engine that manages optimal operation of the three blocks All the key application parameter of the device are stored into an internal NVM non volatile memory allowing wide configurability and calibration This user manual goes in detail through all the NVM parameters and explains how to set them in a real application For any other information about STNRG011A pro...

Page 2: ...document The user can modify them to adapt the STNRG011A algorithms to his application 1 3 GUI application In order to easily program the NVM during the development of a new application a graphical user interface GUI has been developed The GUI strictly works with a communication interface board and allows real time monitoring of the device NVM and EEPROM contents checking and programming For more ...

Page 3: ...on is calculated at each line valley i e input mains zero crossing The device uses the following formula to calculate the power Equation 2 pinn 2 Kp Ki 1 1 z 1 err 2 where err is equal to the voltage error target output voltage real output voltage divided by VerrLSB 0 473 V 2 2 LLC The LLC compensation is based on an analog circuitry at the secondary side The time shift value applied by the contro...

Page 4: ...efault value is disabled i e patching disabled The user has to maintain the patching feature disabled if no EEPROM is installed on the application 3 1 3 ATE mode Size 1 bit Enables disables the ATE mode Available values are Enabled Disabled Use The ATE mode is required to read write the NVM Therefore this parameter should be set to Enabled In case after the correct programming of all NVM parameter...

Page 5: ...se of device shutdown becomes an output and goes to 5 V The duration of the pulse depends on the shut down cause For the normal shutdown i e mains removal brown out event OLP and PFC UVP faults the pulse is 5 ms long normal pulse During this time the PFC is stopped while the LLC is still working keeping the output voltage regulated In case of a dangerous fault both PFC and LLC stages are immediate...

Page 6: ...ion and protection reactiveness The value 1 can be used if minimum intervention time is required in this case pay attention because some noise could trigger the protection Higher values can be used in case of noisy boards in this case the reaction to real OCP2 events will be slower 3 2 4 PFC HW OVP detection Size 1 bit Enable disable the hardware PFC OVP comparator Available values are Disabled En...

Page 7: ...hold is 2 5 V 3 2 8 Disconnection faults detection Size 1 bit Enables disables the feedback disconnections faults detection Available values are Disabled Enabled Use It is suggested to enable the feedback disconnection faults detection Note Disconnection faults have always latched behavior 3 2 9 PFC OC2 behavior Size 1 bit Sets the behavior of PFC OC2 protection Available values are Not latched La...

Page 8: ...he system work with a low bulk voltage Please remember that because of the LLC OC2 protection and the ACP feature the system is still protected against overstresses 3 2 12 LLC SS timeout behavior Size 1 bit Sets the behavior of the LLC soft start timeout protection Available values are Not latched Latched If the fault is set as Not latched the system will try to restart after the time defined by t...

Page 9: ...VCC will remain between 15 V and 17 V using the HV start up generator as long as there is the mains connected 3 2 16 LLC OVP behavior Size 1 bit Sets the behavior of the LLC OVP Available values are Not latched Latched If the fault is set as Not latched the system will try to restart after the time defined by the Non latched faults timer parameter If the fault is set as Latched the switching activ...

Page 10: ...ing to design requirements The middle value 267 ns can be used as a starting point and then after looking at the PFC_CS waveform during the PFC operation it can be adjusted 3 3 4 PFC THD improver base Size 3 bits Sets the base value for the ReCOT functionality THD improver Available values are 0 mV 2 mV 4 mV 6 mV 8 mV 10 mV 12 mV 14 mV The parameter sets the PFC_CS comparator threshold Use This pa...

Page 11: ...ain πflineRsense 6 Use Together with the PFC THD improver base this parameter can be used to improve the distortion and power factor of the PFC The value can be initially calculated with Equation 6 to compensate for the capacitance at the PFC input and EMI filter and then tune it by observing the current waveform at the converter input and THD PF measurements to find the optimum point 3 3 6 PFC ma...

Page 12: ...Figure 1 STNRG011A GUI circled in red the raw value of the input power 3 3 7 PFC pss Size 3 bits Sets the PFC power during the soft start Available values are 640 1280 1920 2560 3200 3840 4480 5120 The higher the value the higher the on time of the PFC MOSFET during the soft start phase Use Choose the value that allows reaching the required PFC soft start time The faster the soft start time requir...

Page 13: ...ameter is mainly used to guarantee a fast reaction to transients forcing the PFC to increase the number of valleys or switch to DCM when the internal power value plus nValleys PFC Delta Pin Vskip is lower than this parameter The frequency based mode change measures the frequency at each half line cycle then if the frequency is out of the PFC Min Tsw Vskip or PFC Max Tsw Vskip values it increments ...

Page 14: ...Min Tsw Vskip or PFC Max Tsw Vskip values it increments or decrements the number of valleys by one By only relying on the frequency it would require 4 half line cycles to change from DCM to TM potentially causing a dip on the Vbus The threshold should be kept high enough so that in the steady state the frequency dominates the mode change 3 3 11 PFC Delta Pin Vskip Size 5 bits Sets a correction fac...

Page 15: ...ze 5 bits Sets the minimum switching period i e the maximum switching frequency for the valley skipping mode Available values are 234 kHz 221 kHz 208 kHz 197 kHz 188 kHz 179 kHz 170 kHz 163 kHz 156 kHz 150 kHz 144 kHz 139 kHz 134 kHz 129 kHz 125 kHz 121 kHz 117 kHz 110 kHz 104 kHz 99 kHz 94 kHz 89 kHz 85 kHz 82 kHz 78 kHz 75 kHz 72 kHz 69 kHz 67 kHz 65 kHz 63 kHz 60 kHz The period is measured at t...

Page 16: ...kHz 39 kHz 37 kHz 36 kHz 34 kHz 33 kHz 32 kHz 31 kHz 30 kHz 29 kHz The period is measured at the peak of the mains sinusoidal voltage If the measured period is higher than this value the system decreases the number of valleys towards TM The corresponding frequency values are shown above Use This value together with the PFC Min Tsw Vskip is used to set the range of PFC switching frequency therefore...

Page 17: ...rameter to 0 disables the skipping area feature in case good THD and PF are required even at very low loads 3 3 16 PFC Vout target Size 3 bits Sets the nominal PFC output voltage Available values are 1 946 V 377 V 1 965 V 381 V 1 985 V 385 V 2 004 V 388 V 2 024 V 392 V 2 063 V 400 V 2 102 V 407 V 2 141 V 415 V This is the voltage level at which the PFC stage regulates its output in all operating c...

Page 18: ...put voltage 3 3 18 PFC UVP threshold delta Bits 3 Sets the UVP level for PFC output voltage Available values are 0 156 V 30 V 0 234 V 45 V 0 313 V 61 V 0 391 V 76 V 0 469 V 91 V 0 547 V 106 V 0 625 V 121 V 0 703 V 136 V Use The above values are intended as a negative delta with respect to the PFC Vout target parameter In fact the UVP threshold is defined as Equation 10 PFC UVP threshold PFC Vout t...

Page 19: ...red when the system is approaching the capacitive mode i e the time between the MOSFET turn on and tank current zero crossing becomes smaller than the value programmed with the parameter Soft ACP entering threshold The feature will try to recover the capacitive mode reducing the LLC time shift value of a quantity defined by the Soft ACP TS decrement every time the protection is triggered for a max...

Page 20: ...ift for the first low side gate drive pulse during the safe start Such time shift value is then used as the first one for the LLC soft start 3 4 4 LLC dead time Size 2 bits Sets the LLC half bridge dead time Available values are 266 7 ns 333 3 ns 400 ns 466 7 ns Use this parameter to select the dead time duration for both transitions according to resonant tank needs 3 4 5 LLC soft start speed Size...

Page 21: ...t value is used to set the maximum LLC switching frequency The relationship between the time shift and switching period is complex Anyway for this limit condition a good approximation can be found see Figure 2 Figure 2 LLC operation at fSW fRES When the operating frequency is much higher than the resonance frequency the resonant tank current ILLC becomes a triangular waveform because the current p...

Page 22: ...em is well designed and guarantees the ZVS operation 3 4 7 Maximum time shift Size 4 bits Sets the maximum value for the time shift during the normal operation Available values are 3 96 μs 4 33 μs 4 49 μs 4 76 μs 5 02 μs 5 29 μs 5 56 μs 5 82 μs 6 09 μs 6 36 μs 6 62 μs 6 89 μs 7 16 μs 7 42 μs 7 69 μs 7 96 μs Use The maximum time shift value is used to set the minimum LLC switching frequency The rel...

Page 23: ...ion 15 ZCDdelay ZCD_compdel LLC ZCD comp digital filtering 15 ZCD_compdel is the comparator delay estimated in 150 ns LLC ZCD comp digital filtering is the digital filtering of the ZCD comparator This formula can be used to start the design and the value can be fine tuned at the bench running the real application prototype Remember that the STNRG011A provides anti capacitive protection ACP so even...

Page 24: ...es are 8 16 This parameter defines the maximum consecutive number of times the LLC OC1 is triggered before shutting down If the frequency based management is selected in case LLC OC1 comparator is triggered the device increases the frequency of the LLC in case the maximum OLP occurrence is reached the device is shut down entering the OLP fault state that can be programmed as latched or not latched...

Page 25: ...or Note In case the hard ACP detection is disabled the system will not shutdown if ACP is sensed during dead time but it will wait for the correct ZCD sign in order to turn on the next gate drive 3 4 14 Soft ACP entering threshold Size 3 bits Sets the time threshold for entering the soft ACP management Available values are 100 ns 167 ns 233 ns 300 ns 367 ns 433 ns 500 ns 567 ns Use If the time bet...

Page 26: ... can be latched or not latched depending on the LLC ACP behavior parameter 3 5 Burst mode parameters 3 5 1 External burst mode Size 1 bit Enables disables the external burst mode feature Available values are Disabled Enabled Use The external burst mode feature is used to drive the burst mode through an external signal The feature enables disables the external BM comparator active on the LLC_AUX pi...

Page 27: ... external or LLC_FB pin driven must be asserted for the time defined by this parameter This allows reject noise on LLC_FB and LLC_AUX pins 3 5 4 LLC_FB burst entering thr Size 6 bits Sets the voltage threshold to enter the burst mode Available values are Voltage on LLC_FB pin 268 6 mV 278 3 mV 288 1 mV 297 9 mV 307 6 mV 317 4 mV 327 1 mV 336 9 mV 346 7 mV 356 4 mV 366 2 mV 376 0 mV 385 7 mV 395 5 ...

Page 28: ...d select the closer LLC_FB burst entering thr value from the values on the left If the external burst mode is enabled and the minimum value 268 6 mV is selected the pure external burst mode is activated only the LLC_AUX Ext The BM comparator manages the burst mode entering exiting If the external burst mode is enabled and the minimum value 268 6 mV is NOT selected the hybrid external burst mode is...

Page 29: ...age threshold the equivalent time shift of that voltage is shown The most suitable values are usually 0 75 V or 1 V 3 5 6 LLC_FB burst wake up hyst Size 1 bit Sets the hysteresis for the burst wake up comparator connected to LLC_FB Available values are 5 mV 10 mV Use The best choice is usually 5 mV 3 5 7 Min TS in burst mode Size 5 bits Sets the minimum time shift value during the burst mode Avail...

Page 30: ...ggestion is to use a value that provides good energy transfer in order to have efficient operation For example in systems designed to work at resonance the time shift during the burst mode can be selected to work at resonance or a little below it 3 5 8 Min number of burst pulses Size 4 bits Sets the minimum number of switching cycles inside one burst sequence Available values are 2 3 4 5 6 7 8 9 1...

Page 31: ...a fixed number of switching cycles it could be done by setting the parameter to 0 3 5 10 Min time between burst seq Size 2 bits Sets the minimum time between two burst sequences to increase the number of switching cycles Available values are 5 93 ms 10 2 ms 14 47 ms 18 73 ms During the burst mode if the load is increased and the distance between two bursts reaches the value defined by this paramet...

Page 32: ...nces is reduced If the time distance between two consecutive burst sequences reaches the time threshold set by this parameter the system will exit the burst mode Therefore the lower the value for this parameter the higher the load for exiting the burst mode Please note that this mechanism is not used with the pure external burst mode Use To tune this parameter initially set it to a very low value ...

Page 33: ...1 comp digital filtering delta Size 1 bit Sets the digital filtering for the PFC OC1 comparator Available values are 33 3 ns 166 7 ns Use The digital filter for the PFC OCP1 comparator is defined as a positive delta with respect to the PFC OC2 comp digital filtering parameter Equation 18 PFC OC1 comp digital filtering 18 PFC OC2 comp digital filtering PFC OC1 comp digital filtering delta The digit...

Page 34: ... rising threshold 10 mV higher with respect to any selection of the falling threshold 3 6 8 PFC HW OVP comp digital filtering Size 2 bits Sets the digital filtering for the PFC HW OVP comparator Available values are 4 25 μs 2 12 μs 1 05 μs 516 7 ns 3 6 9 LLC OLP comp digital filtering Size 2 bits Sets the digital filtering for the LLC OC1 comparator for the OLP functionality Available values are N...

Page 35: ...116 7 ns 183 3 ns 250 ns 316 7 ns 383 3 ns 450 ns 516 7 ns Use The filtering has to be chosen considering the trade off between the noise rejection and maximum operating frequency 3 6 12 LLC OVP comp digital filtering Size 2 bits Sets the digital filtering for the LLC OVP comparator Available values are 4 25 μs 2 12 μs 1 05 μs 516 7 ns UM3002 Comparators setting UM3002 Rev 1 page 35 42 ...

Page 36: ...Revision history Table 1 Document revision history Date Version Changes 08 Apr 2022 1 Initial release UM3002 UM3002 Rev 1 page 36 42 ...

Page 37: ...5 3 1 6 Early warning feature 5 3 1 7 EW signal in burst mode 5 3 1 8 Non latched faults timer 5 3 2 Faults parameters 6 3 2 1 Surge detection 6 3 2 2 PFC OC2 detection 6 3 2 3 Max number of PFC OC2 6 3 2 4 PFC HW OVP detection 6 3 2 5 LLC OC2 detection 6 3 2 6 Max number of LLC OC2 7 3 2 7 LLC OVP detection 7 3 2 8 Disconnection faults detection 7 3 2 9 PFC OC2 behavior 7 3 2 10 PFC HW OVP behavi...

Page 38: ...Vout SS end delta 18 3 3 18 PFC UVP threshold delta 18 3 3 19 PFC SW OVP threshold delta 18 3 4 LLC parameters 19 3 4 1 Soft ACP feature 19 3 4 2 LLC HVG first Ton 19 3 4 3 LLC LVG first TS 20 3 4 4 LLC dead time 20 3 4 5 LLC soft start speed 20 3 4 6 Minimum time shift 21 3 4 7 Maximum time shift 22 3 4 8 LLC OLP threshold 23 3 4 9 LLC OLP timeout 24 3 4 10 Maximum OLP occurrences 24 3 4 11 LLC O...

Page 39: ...32 3 5 13 No burst window width 32 3 6 Comparators setting 33 3 6 1 Surge comp digital filtering 33 3 6 2 PFC CS comp digital filtering 33 3 6 3 PFC OC2 comp digital filtering 33 3 6 4 PFC OC1 comp digital filtering delta 33 3 6 5 PFC ZCD comp digital filtering 33 3 6 6 PFC ZCD comp falling thr 34 3 6 7 PFC ZCD comp rising thr 34 3 6 8 PFC HW OVP comp digital filtering 34 3 6 9 LLC OLP comp digita...

Page 40: ...List of tables Table 1 Document revision history 36 UM3002 List of tables UM3002 Rev 1 page 40 42 ...

Page 41: ...of figures Figure 1 STNRG011A GUI circled in red the raw value of the input power 12 Figure 2 LLC operation at fSW fRES 21 Figure 3 LLC operation at fSW fRES 23 UM3002 List of figures UM3002 Rev 1 page 41 42 ...

Page 42: ...ts and ST assumes no liability for application assistance or the design of purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST For additional information about ST...

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