ST STM8L1526-EVAL, User Manual, Page: 19 / 46

STM8L1526-EVAL Hardware layout and configuration
Doc ID 15437 Rev 1 19/46
Figure 9. STM8L1526-EVAL IDD Halt mode measurement timing diagram
The Halt mode measurement procedure can be used in Halt mode and slow or fast active
Halt modes if the IDD current does not exceed 12 uA else the Run measurement procedure
should be used up to 12 mA.
2.16 Comparator
Three I/Os are used to implement a comparator feature to be used as low precision ADC in
Figure 10 .
●
Comparator noninverting input PD1 connected to the reference capacitor (Cref).
●
One I/O PE0 used as output, connected to the reference resistor (Rref) used to charge
Cref.
●
Comparator inverting input used as ADC input PC7 to be connected to the
potentiometer.
Figure 10. STM8L1526-EVAL low precision ADC based on comparator
0 150mS 300mS 450mS
MCU mode
Run
Halt
Wake-up IDD Measure
Halt mode IDD measurement timing
Q13 = LP_WAKEUP
(PE6)
Clear CNT
IDD_CNT_EN (PE7)
Q12= LOW _POW ER_EN
(T3 pin 3)
Q13n = U21 pin 4
1 2
Cref
1 2
P1
10K
GND
VDD_ADJ
GND
1
2
Rr
ef
PE5
COMP2
TIM2/3
12
11
5
4
6
+
-
COMP2A
PD0
PE0
PD1
CMP_Rref
PC3
PC4
CMP_Cref
PC7
VREFINT 1.2V