The
hosts two
in a 16-lead QFN package to reach a 12-input array. The device
enables industrial inputs to meet type 1 and 3 characteristic of IEC 61131-2 standard, while the IC complies with
the following standards:
•
IEC 61000-4-2 level 1: ±4 kV (air discharge)
•
IEC 61000-4-2 level 1: ±2 kV (contact discharge)
1.5.3
ISO8200AQ
The
is a galvanic isolated 8-channel driver featuring a very low supply current. It embeds two
independent galvanic isolated voltage domains (V
CC
and V
DD
for process and control logic stages, respectively).
The IC is designed to drive any kind of load (inductive, resistive or capacitive) with one side connected to ground.
The control logic stage features an 8-bit output status register (where the microcontroller sets the ON/OFF status
of the output channels in the process stage) and an 8-bit fault register (where the OVT faults of each channel are
stored). The two stages communicate through the galvanic isolation channel via an ST proprietary protocol.
Active channel current limitation (OVL) combined with thermal shutdown (OVT), independent for each channel,
protects the device against overload and overtemperature. Additional embedded functions include loss of ground
protection, V
CC
and V
DD
UVLOs (with hysteresis), watchdog and V
CC
PGOOD.
An internal circuit provides an OR-wired not latched common (FAULT) indicator signaling the channel OVT. The
PGOOD diagnostic pin is activated if V
CC
falls below the power good internal threshold. Both FAULT and PGOOD
pins are open drain, active low, fault indication pins.
The device is UL1577 certified and is designed to meet IEC 61000-4-2, IEC 61000- 4-4, IEC 61000-4-5 and IEC
61000-4-8 standards. The package is TFQFPN32.
1.5.4
IPS4260L
The
is a monolithic high speed (F
SW
up to 250 kHz) device, which can drive four independent
capacitive, resistive, or inductive loads with one side connected to the supply voltage. The channels can be
paralleled to reduce power dissipation.
When connected to V
CC
rail, four integrated catch diodes clamp the turn-off transients generated by inductive
loads even with huge inductance; combined with proper external TVS connected to V
CC
or to GND the IC allows
fast decay, too. Each channel is protected against overload or short-circuit: the intervention level can be set
by an external resistor on I
LIM
pin (see device data sheet for details). Built-in thermal shutdown protects the
chip against overtemperature even in case of short-circuit. If enabled, the integrated cut-off protection features a
non-dissipative protection in case of overload; it limits both the output average current value and, consequently,
the device overheating.
Cut-off delay/restart can be programmed by external resistors on CoD pin; it can be disabled by shorting CoD to
GND. Two common diagnostic open drains pins (OL, for open load and FLT for cut-off and thermal shutdown)
together with the four open drain on each INx pin (cut-off and thermal shutdown) feature an extensive diagnostic
of the chip.
The package is a miniaturized HTTSSOP20 and is designed to meet IEC 61131-2 standard.
1.5.5
STM32F746ZG
The
microcontroller is the core of our evaluation board and is responsible for the management of
all industrial I/O ICs and for the HMI running on the 3.5 display with the TouchGFX technology.
The STM32F746xx devices are based on the high-performance ARM
®
Cortex
®
-M7 32-bit RISC core operating
at up to 216 MHz frequency. The Cortex
®
-M7 core features a single floating point unit (SFPU) precision which
supports all ARM
®
single-precision data-processing instructions and data types. It also implements a full set of
DSP instructions and a memory protection unit (MPU) which enhances the application security.
The STM32F746xx devices incorporate high-speed embedded memories with a Flash memory up to 1 Mbyte,
320 Kbytes of SRAM (including 64 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction
TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and
an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit
multi-AHB bus matrix and a multi-layer AXI interconnect supporting internal and external memories access.
All the MCUs in this family offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen general-purpose
16-bit timers including two PWM timers for motor control and one low-power timer available in stop mode, two
general-purpose 32-bit timers, a true random number generator (RNG). They also feature standard and advanced
communication interfaces. For further details, see the device data sheet.
UM2933
Main components
UM2933
-
Rev 1
page 8/42