UM0819
Configuration and functionality
Doc ID 16379 Rev 2
16/37
PHY MII address
The MDIO/MDC serial management interface is used to access the internal registers of the
PHY. The Ethernet MAC that is connected to the PHY must know the appropriate PHY
address for successful communication. Special case is the PHY address 0x00. If this
address is used as the bootstrap address during the reset, the 00000 value is latched into
the internal receive mode control register RN14 (0x14h) but the PHY goes also to the
isolation mode. It is possible to change the PHY address by writing the RN14 register later
when application is already running.
Power-down
This pin is an active low input of the PHY and should be asserted low to put the device in
a power-down mode. During the power-down mode, TXP/TXN outputs and all LED outputs
are 3-stated, and the MII interface is isolated. The power-down functionality is also
achievable by software by asserting bit 11 of register RN00.
Loopback
Local loopback passes data internally from the transmitting to the receiving serial analog
logic. There are two ways to enter the internal loopback mode, either writing RN00 register,
bit 14 (MDIO/MDC) or by using boot strap LPBK pin (V
DD
- enabled, GND - disabled,
through 2.2 k
Ω
resistor).
Table 1.
Auto-negotiation jumper settings
(1)
1.
See functionality of AN_xxx
pins in the ST802RT1 product documentation.
Jumper
Description
Default configuration
JP16
AN_1
High
JP17
AN_0
High
JP18
AN_EN - Auto-negotiation enable; when “high” - auto-
negotiation enabled, when “low” - auto-negotiation disabled
High
Table 2.
PHY MII address jumper settings
Jumper
Description
Default configuration
JP11
MII address 0
High
JP12
MII address 1
Low
JP13
MII address 2
Low
JP14
MII address 3
Low
JP15
MII address 4
Low
Table 3.
Power-down jumper settings
Jumper
Description
Default configuration
JP1
Power-down, if fitted - PHY works normally; if not fitted - PHY is
in power-down mode
Fitted
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