TEST POINT NAME(TP)
DESCRIPTION
REFERENCE PIN of U2
RESET
I2C Data
Pin 26
SDA
I2C Data
Pin 3
SCL
I2C Clock
Pin 4
DATA_REQ
Data Request Line Input
Pin 28
SDI
Serial Data Input
Pin 5
SCKR
Serial Clock Input
Pin 6
SDO1
Serial Data Output
Pin 9
SCKT
Serial Clock Output
Pin 10
LRCLK
Left/Right Clock Output
Pin 11
OCLK
DAC Oversampling Clock Output
Pin 12
(see figure 4 for details)
1
2
3
4
VDD
GND
SDA
SCL
C12
0.1
µ
F
R8
4.7K
R7
4.7K
VDD
VDD
SDA
SCL
GND
2
3
1
26
OUT_CLK/DATA_REQ
RESET
28
14
VDD
VDD
C11
0.1
µ
F
13
GND
5
SDI
6
SCKR
4
3
2
1
R23
10K
R22
10K
VDD
VDD
7
BIT-EN
8
SRC_INT
JP2
JP1
VDD
24
TESTEN
C8
0.1
µ
F
VDD
23
VDD
22
GND
C1
0.1
µ
F
VDD
16
VDD
15
GND
C2
47pF
C3
47pF
X1 XTAL
R5 1M
21
XTI
20
XTO
R1
0
R3
100
R2
100
J3
SMB
VDD
17
PVDD
18
PGND
C5
0.1
µ
F
C4
1nF
R14 4.7
R13 4.7
19
FILT
C6
470pF
C7
4.7nF
R4
1K
25
SCANEN
27
RESET
C10
4.7
µ
F
VDD
C9
10nF
SW1
SMD
R6 8.2K
9
SDO
12
OCLK
LRCLKT
SCKT
11
10
SDATA
DEM/SCLK
LRCK
MCLK
C16
10
µ
F
C15
0.1
µ
F
AVCC
7
VA+
R11 2.7K
C17 10
µ
F
R10
56K
C29
680pF
R12 2.7K
R21
56K
C18 10
µ
F
C19
680pF
8
6
5
J1 RCA
J2 RCA
R19 56K
R20 56K
C27 0.33
µ
F
C28 0.33
µ
F
R17
1K
R18
1K
C25 100
µ
F
C26 100
µ
F
AOUTL
AGND
AOUTR
1
2
3
4
8
6
5
7
IN1-
IN1+
IN2+
IN2-
1
2
3
4
C24 100
µ
F
C23 10
µ
F
C22 100
µ
F
C21 0.1
µ
F
GND
R16 4.7
C20 0.1
µ
F
OUT1
VCC
OUT2
AVCC
4
PHONEJACK STEREO
J5
TDA2822D
CS4331-KS
U3
STA013
JP3
AMP
U1F
OUTL
OUTR
U1E
J6
EXT
D1
RED
74LVX04
74LVX04
R24
330
74LVX04
74LVX04
74LVX04
74LVX04
U1B
U1A
U1D
U1C
11
13
2
4
6
8
12
3
9
10
1
5
L1
ferrite
R9 470
AMP6 2 ways
J4
AVCC
VDD
1
2
ALL GROUNDS
CONNECTED AT ONLY ONE
POINT BENEATH THE BOARD
D2
GREEN
2.7V/3.3V
C13
47
µ
F
C14
0.1
µ
F
D98AU935A
R26
4.7K
R27
4.7K
U2
U4
TP
TP
TP
7
5
11
9
8
6
13
12
10
14
TP
TP
VDD
C30
0.1
µ
F
GND
TP
TP
TP
TP
TP
R15 4.7
Figure 4. STA013EVB Electrical Schematic
AN1090 APPLICATION NOTE
5/17
