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ST ST802RT1A, Operation Manual

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ST802RT1A, ST802RT1B

Registers and descriptors description

Doc ID 17049 Rev 1

17/58

6 

Registers and descriptors description

All of the management data control and status registers in the ST802RT1x's register set are 
accessed via a Write or Read operation on the serial MDIO port. This access requires a 
protocol described in the MII management interface section.

6.1 Register 

list

         

Table 8.

List of registers

Address

Reg. 

Index

Name

Default 

value

Register description

00h – 0d

RN00

CNTRL

0x0000

Control register

01h – 1d

RN01

STATS

0x7849

Status register

02h – 2d

RN02

PHYID1

0x0203

PHY identifier register Hi

03h – 3d

RN03

PHYID2

0x8461

PHY identifier register Lo

04h – 4d

RN04

LDADV

0x05E1

Auto-negotiation advertisement register

05h – 5d

RN05

LPADV

0x0000

Auto-negotiation link partner ability register

06h – 6d

RN06

ANEGX

0x0004

Auto-negotiation expansion register

07h – 7d

RN07

LDNPG

0x2001

Auto-negotiation next page transmit register

08h – 8d

RN08

LPNPG

0x0000

Auto-negotiation link partner received next page register

Extended registers

10h – 16d

RN10

XCNTL

0x1200

RMII-TEST control register

11h – 17d

RN11

XSTAT

0x0000

Receiver configuration information and interrupt status register

12h – 18d

RN12

XRCNT

0x0100

Receiver event interrupts register

13h – 19d

RN13

XCCNT

0x0140

100Base-TX control register

14h – 20d

RN14

XDCNT

0x000A

Receiver mode control register

18h – 24d

RN18

AUXCS

0x0027

Auxiliary control register

19h – 25d

RN19

AUXSS

0x0000

Auxiliary status register

1Bh – 27d

RN1B

AUXM2

0x000A

Auxiliary mode 2 register

1Ch – 28d

RN1C

TSTAT

0x0820

10Base-T error and general status register

1Eh – 30d

RN1E

AMPHY

0x0000

Auxiliary PHY register

Shadow registers

1Fh - 31d

RN1F

BTEST

0x0000

Shadow Registers enable register

1Bh - 27d

RS1B

AUXS2

0x0000

MISC/status/error/test shadow register

Summary of Contents for ST802RT1A

Page 1: ...Factory automation High end peripherals Building automation Telecom infrastructure Description The ST802RT1x is a high performance fast Ethernet physical layer interface for 10Base T 100Base TX and 10...

Page 2: ...description 18 7 Device operation 38 7 1 100Base TX transmit operation 38 7 2 100Base TX receive operation 39 7 3 10Base T transmit operation 40 7 4 10Base T receive operation 40 7 5 Loop back operat...

Page 3: ...44 7 17 RMII interface 44 7 18 FX mode operation 45 7 19 FX operation detect circuit 45 7 20 PECL transmitter 46 7 21 PECL receiver 47 7 22 Far end fault 48 7 23 MII management interface 48 8 Electric...

Page 4: ...0d08 0x08 Auto negotiation link partner received next page register 26 Table 19 RN10 0d16 0x10 RMII TEST control register 27 Table 20 RN11 0d17 0x11 Receiver configuration information and interrupt st...

Page 5: ...RT1A 9 Figure 5 Pin configuration ST802RT1B 10 Figure 6 LED connections 42 Figure 7 Transmit isolation 44 Figure 8 PECL levels 46 Figure 9 Implementation of the PECL TX section 47 Figure 10 Implementa...

Page 6: ...ceive filters and adaptive equalizer Provides loop back modes for diagnostics Built in stream cipher scrambler de scrambler and 4B 5B encoder decoder Supports external transformer with a turn ratio of...

Page 7: ...ER LEDS HW CONFIG TXP TXN RXP RXN REGISTERS TX_CLK TXD 3 0 TX_EN MDIO MDC COL CRS CRS_DV RX_ER RX_DV RXD 3 0 RX_CLK LEDS HW PROG PINS Serial management MDI MDIX MII RMII INTERFACES 10BASE T 100BASE TX...

Page 8: ...System and block diagrams ST802RT1A ST802RT1B 8 58 Doc ID 17049 Rev 1 3 System and block diagrams Figure 2 System diagram of the ST802RT1A B Figure 3 System diagram of the ST802RT1B in FX mode...

Page 9: ..._LINK AN_EN LED_SPEED AN0 LED_ACT AN1 36 35 34 33 32 31 30 29 28 27 26 25 36 35 34 33 32 31 30 29 28 27 26 25 TXD3 MII_CFG1 GND TXD2 SCLK TX_CLK LPBK_EN TX_EN GNDA VCCA TXD0 TXD1 1 2 3 4 5 6 7 8 9 10...

Page 10: ...EN LED_SPEED AN0 LED_ACT AN1 36 35 34 33 32 31 30 29 28 27 26 25 36 35 34 33 32 31 30 29 28 27 26 25 TXD3 MII_CFG1 GND TXD2 SCLK TX_CLK LPBK_EN TX_EN GNDA VCCA TXD0 TXD1 1 2 3 4 5 6 7 8 9 10 11 12 1 2...

Page 11: ...und 12 GND Ground Digital ground 13 VCCA Supply Analog power supply 14 RXN I O Differential receive inputs 15 RXP I O Differential receive inputs 16 GNDA Ground Analog ground 17 TXP I O Differential t...

Page 12: ...RXER_RXD4 O Receive error receive data 4 41 DVDD Supply Digital power 3 3 V 42 RXD3 PHYADDR4 O S PD Receive data MII Phy4 43 RXD2 PHYADDR3 O S PD Receive data MII Phy3 44 RXD1 PHYADDR2 O S PD Receive...

Page 13: ...MII receive clock This continuous clock provides reference for rxd rx_dv and rx_er signals 25 MHz for 100 Mbps operation 2 5 MHz for 10 Mbps operation 46 COL O MII collision detection The ST802RT1x as...

Page 14: ...Mode 1 and Mode 2 this pin indicates the status of the link The LED is ON when the link is good 27 LED_SPEED O PU Speed LED This pin is driven on continually when 10Mb s or 100Mb s network operating...

Page 15: ...e internal pull downs the default values are 0 See Table 6 for details and configurations 28 27 26 AN_EN AN_0 AN_1 S PU Auto negotiation enable When high this enables auto negotiation with the capabil...

Page 16: ...line PECLHIGH PECLHIGH Undefined state PECLLOW PECLMID PECLHIGH FX mode asserted link OK and data valid Table 6 MII_CFG0 MII_CFG1 configuration mii_cfg0 mii_cfg1 MII mode 0 X RMII mode 1 0 Reserved 1...

Page 17: ...ty register 06h 6d RN06 ANEGX 0x0004 Auto negotiation expansion register 07h 7d RN07 LDNPG 0x2001 Auto negotiation next page transmit register 08h 8d RN08 LPNPG 0x0000 Auto negotiation link partner re...

Page 18: ...trap RW 13 Speed selection 1 100 Mb s 0 10 Mb s Ignored if auto negotiation is enabled Strap RW 12 Auto negotiation enable 1 Auto negotiation is enabled 0 Auto negotiation is disabled Bits 8 and 13 of...

Page 19: ...to negotiation can be disabled by one of two methods hardware or software control If the AN_EN input pin is driven to 0 auto negotiation is disabled by hardware control If bit 12 of the control regist...

Page 20: ...en read Full duplex By default the ST802RT1x powers up in half duplex mode The chip can be forced into full duplex mode by writing a 1 to bit 8 of the control register while auto negotiation is disabl...

Page 21: ...ess completed registers 4 5 6 are now valid 0 Auto negotiation process not completed Active only if auto negotiation is enabled else 0 0 RO 4 Remote Fault 1 Remote fault condition detected 0 No remote...

Page 22: ...if the link pass state has been entered again Jabber detect 10BASE T operation only The ST802RT1x returns a 1 on bit 1 of the status register if a jabber condition has been detected After the bit is...

Page 23: ...w the user to customize the ability information transmitted to the link partner The default value for each bit reflects the abilities of the ST802RT1x By writing a 1 to any of the bits the correspondi...

Page 24: ...the value to this register and does not act upon it Table 15 RN05 0d05 0x05 Auto negotiation link partner ability register Bit Bit name Description Default RW type Type 15 LP Next Page 1 Link partner...

Page 25: ...a 1 when the link partner has next page capabilities It has the same value as bit 15 of the link partner ability register Page received Bit 1 of the auto negotiation expansion register is latched hig...

Page 26: ...essage received 0 Local device cannot comply with message 0 RW 11 Toggle 1 Previous transmitted LCW toggle was 0 0 Previous transmitted LCW toggle was 1 Updated by auto negotiation state machines 0 RO...

Page 27: ...value Table 19 RN10 0d16 0x10 RMII TEST control register Bit Bit name Description Default RW type Type 15 14 RESERVED 000b RO 13 RESERVED 000b RW 12 11 RESERVED 10b RO 10 RESERVED 0b RW 9 MII Enable...

Page 28: ...g interrupt 1 Auto negotiation completed interrupt is pending 0 Auto negotiation not yet completed Interrupt enabled by RN12 6 0 RO LH 5 Remote fault interrupt 1 Remote fault condition interrupt is pe...

Page 29: ...TED INTERRUPT ENABLE 1 Interrupt enabled 0 Interrupt disabled 0 RW 5 REMFLT_DET_EN REMOTE FAULT INTERRUPT ENABLE 1 Interrupt enabled 0 Interrupt disabled 0 RW 4 LK_DWN_EN LINK FAIL INTERRUPT ENABLE 1...

Page 30: ...0 RW 4 2 CMode 000 Auto negotiation running 001 10Base T half duplex 010 100Base TX half duplex 011 Not used 100 Not used 101 10Base T full duplex 110 100Base TX full duplex 111 Transmit isolation 00...

Page 31: ...clock when MDIO interface is idle 0 Normal operation 0 RW 3 0 RESERVED 0111b RO Table 25 RN19 0d25 0x19 Auxiliary status register Bit Bit name Description Default RW Type Type 15 Auto Negotiation comp...

Page 32: ...d received updated on read 0 LCW not yet received 0 RO LH 4 Link Partner Auto Negotiation Able 1 LP supports auto negotiation updated on read 0 LP does not support auto negotiation 0 RO 3 SP100 indica...

Page 33: ...B Auxiliary mode 2 register Bit Bit name Description Default RW Type Type 15 12 RESERVED 0000b RO 11 10 RESERVED 00b RW 9 LED Mode 1 led_link pad ON for link_up BLINK for activity led_speed pad ON for...

Page 34: ...it Bit name Description Default RW Type Type 15 14 RESERVED 00 RW 13 MDIX Status 1 MDI X configuration used 0 MDI configuration used 0 RO 12 MDIX Swap 1 MDIX force if not in fx_mode 0 Normal operation...

Page 35: ...led 0 Normal operation Self cleared after 21MHz clock periods auto negotiation is started Same as RN00_CNTRL 9 0 RW SC 7 Auto Negotiation complete 1 Auto negotiation process completed 0 Auto negotiati...

Page 36: ...lete This read only bit returns a 1 after the auto negotiation process has been completed It remains 1 until the auto negotiation is restarted a link fault occurs or the chip is reset If auto negotiat...

Page 37: ...10 LED Test control 1 LED frequencies up by 8192 times 0 Normal operation 0 RW 9 Descrambler Locked 1 Descrambler locked on RX stream 0 Descrambler not locked 0 RO 8 False Carrier Detect 1 False carri...

Page 38: ...mpled by the device on the rising edge of Tx clk and passed to the 4B 5B encoder to generate the 5B code group used by 100Base TX Idle code groups In order to establish and maintain the clock synchron...

Page 39: ...er MLT3 signals the device converts the MLT3 to NRZI code for further processing The compensated NRZI signals at 125 MHz are then passed to the phase lock loop circuits to extract the original data an...

Page 40: ...lated from the media In 100Base TX internal loop back operation the data comes from the transmit output of the NRZ to NRZI converter then loop back to the receive path into the input of NRZI to NRZ co...

Page 41: ...TX and 10Base T circuits are separated the ST802RT1x can turn off the circuit of either the 100Base TX or 10Base T when the other one is operating There is also a power down mode which can be selected...

Page 42: ...e 4 Pin functions of the ST802RT1x Link LED On when 100 M or 10 M link is active It also blinks at 10 Hz for transmit and receive Speed LED 100 Mbps on or 10 Mbps off Activity LED Blinks at 20 Hz when...

Page 43: ...3 Preamble suppression Preamble suppression mode in the ST802RT1x is indicated by a 1 in bit six of the RN01 register and controlled by bit 1 in the RN14 register If it is determined that all PHY devi...

Page 44: ...urs to allow FLP NLP to be transmitted and received in the event that the external cable connections have been swapped 7 17 RMII interface The reduced media independent interface RMII provides a low c...

Page 45: ...forced in base T mode The data flow for 100BASE FX is Serialized data NRZI encoding multimode DAC PECL format To allow the detection of remote fault conditions in 100BASE FX the IEEE 802 3 standard fa...

Page 46: ...terface and NRZ to NRZI converter and to transmit it to the optical transceiver In this case the data is received by the transmitter in a CMOS format and is transmitted to the optical portion in a PEC...

Page 47: ...rtion The data is sampled by the optical transceiver but the data stream is related to the clock of the transmitting transceiver so it needs to be recovered re sampled and aligned to the RX clock This...

Page 48: ...lock signal The MDIO pin has an internal pull up used to keep the line to logic 1 when not driven Register read write operations are performed sending on the MII Management interface frames in the for...

Page 49: ...A IDDQD Quiescent current digital 4 5 mA VIH Input high voltage 1 95 V VIL Input low voltage 0 85 V 10Base T voltage current characteristics Vida10 Input differential accept peak voltage 5MHz 10MHz 58...

Page 50: ...t 17 33 Tflpw FLP width 100 00 ns Tflcpp Clock pulse to clock pulse period 111 125 139 s Tflcpd Clock pulse to data pulse period 55 5 62 5 69 5 s Tflbw Burst width 2 ms Tflbp FLP burst period 8 16 24...

Page 51: ...ST802RT1A ST802RT1B Electrical specifications and timings Doc ID 17049 Rev 1 51 58 Figure 11 Normal link pulse timings Figure 12 Fast link pulse timing...

Page 52: ...Electrical specifications and timings ST802RT1A ST802RT1B 52 58 Doc ID 17049 Rev 1 Figure 13 MII management clock timing...

Page 53: ...ical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade...

Page 54: ...Doc ID 17049 Rev 1 Table 36 LQFP48 mechanical data Dim mm Min Typ Max A 1 60 A1 0 05 0 15 A2 1 35 1 4 1 45 b 0 17 0 22 0 27 c 0 09 0 20 D 8 80 9 9 20 D1 6 80 7 7 20 D3 5 50 E 8 80 9 9 20 E1 6 80 7 7...

Page 55: ...ST802RT1A ST802RT1B Package mechanical data Doc ID 17049 Rev 1 55 58 Figure 14 Dimensions of the LQFP48 package 0110596...

Page 56: ...Package mechanical data ST802RT1A ST802RT1B 56 58 Doc ID 17049 Rev 1 Figure 15 LQFP48 footprint recommended data mm...

Page 57: ...ST802RT1A ST802RT1B Revision history Doc ID 17049 Rev 1 57 58 10 Revision history Table 37 Document revision history Date Revision Changes 02 Feb 2010 1 Initial release...

Page 58: ...LIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGH...

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