L6482
Phase current control
Doc ID 023768 Rev 1
39/73
Figure 21.
Fast decay tuning during the falling steps
7.4
Torque regulation (output current amplitude regulation)
The phase currents are monitored through two shunt resistors (one for each power bridge)
connected to the respective sense pin (see
). The integrated comparator
compares the sense resistor voltage with the internal reference generated using the peak
value, which is proportional to the output current amplitude, and the microstepping code.
The comparison result is provided to the logic in order to implement the current control
algorithm as described in previous sections.
The peak reference voltage can be regulated in two ways: writing TVAL_ACC, TVAL_DEC,
TVAL_RUN and TVAL_HOLD registers or varying the ADCIN voltage value.
The EN_TQREG bit (CONFIG register) sets the torque regulation method. If this bit is high,
ADC_OUT prevalue is used to regulate output current amplitude (see
). Otherwise the internal analog-to-digital converter is at the user’s disposal
and the output current amplitude is managed by TVAL_HOLD, TVAL_RUN, TVAL_ACC and
TVAL_DEC registers (see
,
The voltage applied to the ADCIN pin is sampled at fS frequency and converted in an NADC
bit digital signal. The analog-to-digital conversion result is available in the ADC_OUT
register.
F
a
lling
s
tep
1
s
t
f
as
t dec
a
y:
t
FALL
= FALL_
S
TEP/4
F
a
lling
s
tep
1
s
t
f
as
t dec
a
y:
t
FALL
= FALL_
S
TEP/2
2
nd
f
as
t dec
a
y:
t
FALL
= FALL_
S
TEP/2
Time
reference c
u
rrent
AM15052v1
