Block descriptions
UM1585
Doc ID 023872 Rev 1
On the expansion connectors it is possible, through JP2, to select NAND_VDD between
3.3 V and 1.8 V to test different voltage devices. The NAND FLASH SPEAr I/O voltage has
to be aligned with the Flash device voltage. Use JP2, JP3 and Strapping option SW4.1 to
set the correct voltage.
Figure 7.
NAND Flash device voltage selector
Figure 8.
SPEAr NAND Flash I/O voltage selector
4.4 PCIe/SATA
The SPEAr1310 rev. C device has up to 3 PCIe or 3 SATA interfaces. The
EVALSP1310CPU board provides the following configuration: one standard SATA and two
PCIe Gen2 lanes.
The lane (PHY1) is used as a PCIe endpoint. In the default setting, the PCIe endpoint is not
available. To make the PCIe endpoint available it is necessary to change the settings of the
board removing the 0 ohm resistors, R90 and R91 and installing 0 ohm resistors, R92 and
R93. The lane PHY0 is used as SATA and on board there is a standard connector (J3).
SPEAr MIPHY PLL can be powered by an internal regulator or can use external power.
JP24 has to be configured according to the JP5 setting.
Figure 9.
SPEAr MIPHY PLL power selectors
4.4.1 PCIe
clock
The PCIe clock is generated by ICS557-03 (differential clock generator). This device can
generate 2 different clock frequencies. This depends on the settings of bits S2 to S0.
26
NFnWP
27
NFnWE
Table 3.
J1 NAND expansion connector pin assignment (continued)
JP2
1
3
3.3 V
2
JP2
1
3
2
1.8 V
JP3
1
3
3.3 V
2
JP3
1
3
1.8 V
2
JP24
1
2
External
(closed)
JP5
1
3
External
2
JP5
1
3
Internal
2
JP24
1
2
Internal
(closed)