ST EVALSP1310CPU User Manual Download Page 10 | Manualshive

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ST EVALSP1310CPU User Manual Download Page 10

Getting started

UM1585

Doc ID 023872 Rev 1

It is possible to simulate a cross cable by changing the position of the J17 jumpers as shown
below.

Refer to the schematic drawing (contact your local ST representative for availability), for the
pin-out of the connectors.

Figure 4.

Serial cable setting (J17)

3.4 Reset

switch

A manual reset switch (P1) is available on the top side of the board.

Cross

cable

J17

1

2

3

4

J17

1

2

3

4

modem

cable

Null

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Summary of Contents for EVALSP1310CPU

Page 1: ...ily act as a learning tool for rapid familiarity with the features of the SPEAr1310 rev C provide a reference design to use as a starting point for the development of a final application board The EVA...

Page 2: ...ck descriptions 11 4 1 General power supply 11 4 1 1 Power LEDs 12 4 2 Dynamic memory subsystem 12 4 3 Static memory subsystem 13 4 3 1 Serial Flash 13 4 3 2 NAND Flash 13 4 3 3 NAND Flash expansion 1...

Page 3: ...7 RTC battery connector 21 8 Expansion connectors 22 9 Debug interface 24 10 Strapping options 25 11 Test modes 26 12 LEDs 27 13 Jumper descriptions 28 14 Connectors 29 15 Pushbuttons 29 Appendix A L...

Page 4: ...erial Flash M25P64 U1 and M25P40 U3 enable 13 Figure 6 NAND Flash selection 13 Figure 7 NAND Flash device voltage selector 14 Figure 8 SPEAr NAND Flash I O voltage selector 14 Figure 9 SPEAr MIPHY PLL...

Page 5: ...d 17 Table 10 Ethernet LEDs 18 Table 11 USB host LEDs 19 Table 12 OTG micro USB AB LEDs 19 Table 13 J14 20 ADC connector A2D 21 Table 14 Expansion connector functions EXPI mode enabled 22 Table 15 Exp...

Page 6: ...Kit contents UM1585 6 36 Doc ID 023872 Rev 1 1 Kit contents EVALSP1310CPU board AC adapter output voltage 5 V 2A 2 power adapter plugs USA Europe...

Page 7: ...USB AB One 10 100 1000 Ethernet port One SATA connector One PCIe X1 Endpoint One PCIe X1 Root Complex connector One Serial port up to 115 Kbaud Debug ports CPU JTAG CoreSight 8 ADC channels 10 bit 1...

Page 8: ...Features and block diagram UM1585 8 36 Doc ID 023872 Rev 1 2 2 Connectors jumpers and pushbuttons Figure 3 Connector jumper and push button locations top...

Page 9: ...ee Primary Serial cable setting 2 On a host PC running Windows or Linux start the Terminal program 3 Connect the AC adapter to a power outlet 4 Power on the board plug the AC adapter jack into J12 A s...

Page 10: ...he J17 jumpers as shown below Refer to the schematic drawing contact your local ST representative for availability for the pin out of the connectors Figure 4 Serial cable setting J17 3 4 Reset switch...

Page 11: ...onnector J11 Expansion connector VDD1V2 SPEAr core SPEAr_VDD1V2 SPEAr DDR3 interface SPEAr_DDR3_1V2 JP31 JP30 VDD1V5 DDR3 chips SPEAr DDR I O SPEAr_DDR3_1V5 SPEAr RTC RTC_VDD1V5 JP32 JP39 VDD1V8 GigaP...

Page 12: ...and one for ECC Total size available is 4 chips x 32 Mb x 8 x 8 banks 1 Gbyte VDD3V3_HOST PCIe x1 connectors 12V_HOST PCIe x1 connectors Table 1 Common power rails continued Name Use Jumper for curren...

Page 13: ...Flash This block is based on ST NAND Flash NAND02GW3B U4 64 MB bus width x8 If required this chip can be replaced and another can be used To do this deselect the on board Flash by removing jumper JP4...

Page 14: ...Ie endpoint is not available To make the PCIe endpoint available it is necessary to change the settings of the board removing the 0 ohm resistors R90 and R91 and installing 0 ohm resistors R92 and R93...

Page 15: ...spread Not applicable 100 1 0 0 0 5 Down 200 1 0 1 1 0 Down 200 1 1 0 1 5 Down 200 1 1 1 No spread Not applicable 200 Table 5 Switch 1 configuration Pin Description default settings 1 Phy address bit...

Page 16: ...igabit PHY Ethernet voltage selector Three JP are used as DP83865 U5 strapping option JP17 JP18 and JP19 Table 6 Jumper configurations Default Settings Description On Off JP6 JP11 Phy address bit 0 1...

Page 17: ...le 7 DP83865 MAC interface setting JP18 TXCLK_RGMII_SEL1 JP19 CRS_RGMII_SEL0 MAC Interface 0 0 GMII 0 1 GMII 1 0 RGMII HP 1 1 RGMII 3COM JP17 1 2 3 1 JP17 1 2 3 0 0 Clock to MAC output is 25 MHz 1 Clo...

Page 18: ...eived D3 Yellow 100M SPEED AND GOOD LINK LED The LED output indicates that the PHY has established a good link at 100 Mbps In 100BASE T mode the link is established as a result of an input receive amp...

Page 19: ...en LED indicates the presence of VBUS and the red one the current limiter status 5 2 Host LEDs USB host LEDs 5 3 OTG USB One OTG micro USB AB connector is present on the board 5 3 1 SPEAr USB interfac...

Page 20: ...USB 2 0 subsystem UM1585 20 36 Doc ID 023872 Rev 1 Figure 13 SPEAr USB phy power selector JP29 1 2 3 Internal JP29 1 2 3 External...

Page 21: ...umpers and providing different values on pins 1 and 19 makes it possible to reduce the range increasing the granularity For example an input of 1 V on J14 19 and 2 V on J14 1 provides a range of 1 to...

Page 22: ...01 SL D RA J21 P N QFS 026 01 SL D RA mates with QMS 026 01 SL D RA The signals available on the expansion connector are shown in Expansion connector functions Figure 14 Samtec connector Note EXPI mo...

Page 23: ...ugh R328 and remove jumper JP4 Table 15 Expansion connector functions EXPI mode not enabled Pin Description 4 Keyboard 2x2 NAND Flash CE WPRT 8 Keyboard expansion to 6x6 NAND Flash expansion 8 15 33 M...

Page 24: ...box and the external box stores this information in a local buffer This makes it possible to stop the CPU activity in order to analyze the program flow For example if a particular data abort occurs yo...

Page 25: ...ault settings 1 GPIO_A0 OFF See Table 20 Software boot options for description 2 GPIO_A1 ON See Table 20 Software boot options for description 3 GPIO_A2 ON See Table 20 Software boot options for descr...

Page 26: ...forced 0 1 0 0 Boot from UART 115 baud no parity 8 data bits 1 stop bit Note Not available on engineering sample devices ES marking 0 1 0 1 Boot from PCIe device 0 1 1 0 Reserved 0 1 1 1 Boot from US...

Page 27: ...GIG PHY Duplex D2 Yellow GIG PHY link1000 D3 Yellow GIG PHY Link100 D4 Yellow GIG PHY Link10 D5 Yellow GIG PHY Activity D7 Red Host1 Overcurrent D8 Green USB Host1 5V D9 Green USB Host2 5V D10 Red USB...

Page 28: ...0 JP15 3 3 GIGA PHY STRAP7 JP16 3 SPEAr GMII I F VDD default 1 2 closed 3 3 V JP17 3 GMII_COL default 1 2 closed pull up JP18 3 MII_TXCLK_SEL1 default 2 3 closed JP19 3 CRS_RGMII_SEL0 default 2 3 clos...

Page 29: ...ctor J4 PCIe Root complex HOST1 J5 PCIe Endpoint Device J6 12 V_HOST PCIe J7 MIPHY JTAG Connector J8 USB Connector Micro A B OTG J10 USB Connector Type A double J11 QFS 104 RA Expansion connector J12...

Page 30: ...tem Except as provided in this Agreement or in the Demo Product s documentation You may not reproduce the demonstration software or related documentation or modify reverse engineer de compile or disas...

Page 31: ...he remaining provisions of this agreement shall continue with the same force and effect as if such unenforceable or invalid provisions had not been inserted in this Agreement WAIVER The waiver by eith...

Page 32: ...ghts notices included on or embedded in the Licensed Software You agree to prevent any unauthorized copying of the Licensed Software and related documentation RESTRICTIONS Unless otherwise explicitly...

Page 33: ...tion or warranty by ST or alter this disclaimer or warranty and in no additional obligations or liabilities shall arise from ST s providing such information or services ST does not assume or authorize...

Page 34: ...not been inserted in this Agreement WAIVER The waiver by either party of any breach of any provisions of this Agreement shall not operate or be construed as a waiver of any other or a subsequent breac...

Page 35: ...UM1585 Revision history Doc ID 023872 Rev 1 35 36 Revision history Table 25 Document revision history Date Revision Changes 07 Nov 2012 1 Initial release...

Page 36: ...RRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLES...

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