ST EVAL-RHRICL1AFV1 User Manual Download Page 3

2

Common features and parameters

This section describes the features that are in common to the three boards, such as: UVLO, floating ground
configuration, current limitation, analog and digital telemetries, and explains how to customize them by changing
the external components on the board.

2.1

Undervoltage lockout and hysteresis settings

The UVLO and hysteresis can be programmed by a set of three resistors: the R

HYS

, R

UVLO

 and R

V

.

A 220 kΩ resistor is generally used for R

V

, the other two resistors are obtained by the following equations:

RUVLO =

2.5*RV

VTH_ON − 2.5

− K

(1)

RUVLO =

2.5*RV

VTH_OFF − 2.5

− RUVLO

(2)

Where K=150 is a corrective fixed value to be added to 

Eq. (1)

 in order to take into account that during the rising

phase of supply voltage, in the UVLO external resistor divider, R

HYS

 is shorted by a non-ideal switch embedded in

the RHRPMICL1A.

2.2

Gate driving

The driver circuit is designed to drive an external P-channel power MOSFET (connected in high-side
configuration) providing on the Vg pin a voltage signal in the range V

CC

 down to (V

CC

 - 12 V). All the evaluation

boards are equipped with a through-hole socket where the power MOSFET can be easily housed.
When the device is ON and no current limitation is active, the Vg node is pulled down and the gate of the external
MOSFET is internally clamped, about 12 V below the supply voltage V

CC

. When the MOSFET has to be switched

OFF, Vg is brought up to V

CC

.

When the MOSFET is in current limitation mode, the Vg voltage is a value inside the range [V

CC

-12 V, V

CC

],

defined by the limitation control loop.

2.3

Current sense and limitation function

The voltage drop on the external R

SENSE

 resistor is continuously monitored (by ISNS+ and ISNS- pins) and

compared with a fixed 100 mV internally generated threshold.
The current limitation threshold can be externally set according to the application requirements by a suitable
choice of the R

SENSE

 resistor.

In the re-triggerable and latched evaluation boards it is:

ILIM = 100mV/RSENSE

(3)

If the voltage drop on R

SENSE

 exceeds 100 mV means that the current demand is becoming excessive: an

internal timer starts counting the trip-off time T

ON

 and the device enters the current limitation mode. In such a

condition the limitation control loop is enabled in order to force Vg to the proper voltage level, limiting the current
to the load.
Please refer 

Section  5.1.2.2  Bill of material of the EVAL-RHRICL1AFV1 board

 for the current limitation settings

in the foldback mode evaluation board.

2.4

Floating ground configuration

The evaluation boards are equipped with the R

GND

 floating resistance mounted between the GND pin of the ICL

(GND) and the system ground (MGND).
An embedded 14.8 V Zener diode chain allows the device to operate in floating ground configuration and protects
the ICL device as its internal voltage supply is clamped at V

Z

 ~ 15 V (14.8 V typ).

According to the voltage value of the Bus supply and depending on the value of RGND, the device can work (or
not) in floating ground condition, as follows:

UM2605

Common features and parameters

UM2605

 - 

Rev 1

page 3/27

Summary of Contents for EVAL-RHRICL1AFV1

Page 1: ...on Table 1 Application tools Type Part number Configuration Marking Evaluation tools EVAL RHRICL1ATV1 Re triggerable RHRPMICL1ATV1 RE TRIGGERABLE Evaluation tools EVAL RHRICL1ALV1 Latched RHRPMICL1ALV...

Page 2: ...on activation cycle Re triggerable mode after the trip off time that is externally configurable the device switches OFF and remains in this state for a recovery time that is externally configurable On...

Page 3: ...n current limitation mode the Vg voltage is a value inside the range VCC 12 V VCC defined by the limitation control loop 2 3 Current sense and limitation function The voltage drop on the external RSEN...

Page 4: ...roper protection components to the application Guidelines on this feature are provided in the RHRPMICL1A datasheet 2 5 Analog telemetry The analog telemetry circuit gives information about the current...

Page 5: ...Figure 4 Telemetry signals UM2605 Digital telemetry status telemetry UM2605 Rev 1 page 5 27...

Page 6: ...FF 40 V HYS 4 V ILIM 5 A TON 3 ms typ 2 7 ms with TOFF 1s typ 0 94 s The evaluation board schematic is shown below Please note that the capacitor Csns_2 connected in parallel to the RSENSE affects the...

Page 7: ...nd off again while the overload persists hic up mode The trip off time TON is set by the CON capacitor connected between the pins TON and GND and it is calculated by the following equation TON RIR CON...

Page 8: ...Figure 7 Overload shorter than TON TOFF Figure 8 Overload longer than TON TOFF Figure 9 Continuous short circuit UM2605 Operations UM2605 Rev 1 page 8 27...

Page 9: ...3 3 1 Layout of the EVAL RHRICL1ATV1 board Figure 10 EVAL RHRICL1ATV1 top layout Figure 11 EVAL RHRICL1ATV1 bottom layout UM2605 Operations UM2605 Rev 1 page 9 27...

Page 10: ...2 KEMET C1812C273J5G ACTU NPO 1812 10 1 Rv_2 220 k 100 V 0 1 25 ppm C 0 125 W Panasonic ERA6AEB224V 0805 11 2 Rtms _2 Rtms _2 5 k 100 V 0 1 5 ppm C 0 200 W Vishay thin film PNM0805E5001 BST5 0805 12 1...

Page 11: ...nt 22 1 SCH2 STPS3150 3 A 150 V ST STPS3150U Diode 100 V 5 A SMB 23 1 P_ch2 SOCKET P ch TO254AA socket for the STRH40P10 34 A 100 V 3M TOUCH SYSTEMS 203 2737 55 110 2 P channel BVdss 100 V id 48 A RDS...

Page 12: ...V ILIM 2 A TON 10 ms TC_ON and TC_OFF are available on TC3 connector SET_STS can be connected to VCC or GND through the switch SW1 The evaluation board schematic is shown below Please note that the ca...

Page 13: ...ccessible on the RTM and RSTS resistors respectively Figure 13 Testing environment 4 2 2 Trip off time programming In latched mode if the duration of the overcurrent is greater than the trip off time...

Page 14: ...atched evaluation board schematic or in alternative way the device is switched OFF by applying a negative pulse signal of the typical duration of 100 s directly to the pin TC_ON In order to have a mor...

Page 15: ...pm C Panasonic ERA6AEB224V 0 125 W 0805 10 2 Rtms _1 Rtms _1 5 k 100 V 0 1 25 ppm C Vishay thin film PNM0805E5001 BST5 0 200 W 0805 11 1 Rtm_1 100 k 100 V 0 1 25 ppm C Panasonic ERA6AEB104V I 20 A 0 1...

Page 16: ...m Qg 162 nC 24 1 U1 ICL001 FLAT20 ST FLAT20 25 2 N CH1 N CH2 STN1NF101 A 100 V Vgsth 3 V ST STN1NF10 N ch o NPN from 60 V 100 V SOT 223 26 2 Rg_on_1 Rg_off_1 1 k 150 V 1 Vishay CRCW08051K0 0FKEA 125...

Page 17: ...ting down the device in case of failure The pin configuration of the ICL in this operation mode is Telecommand interface disabled TC_ON and TC_OFF both connected to VCC SET_STS is connected to VCC on...

Page 18: ...100nF SET_FLB SET_STS T_OFF ICL_GND I_REF T_ON STS Rsts_3 50k TM 0 HYS UVLO VG UVLO HYS VCC Rg_3 4R7 FOLDBACK MODE Rcomp_3 1k Ctm_3 4 7 pF TC_ON TC_OFF R_flb 107k Ruvlo_3 35 7k Rtm_3 100k Rtms _3 5k...

Page 19: ...back current limiter characteristic This behavior is obtained by adding two sensing resistors RS3 and RS3 between the RSENSE terminals and ISNS and ISNS pins of the RHRPMICL1A device In addition the f...

Page 20: ...re 20 Foldback current limiter characteristic reached when a short circuit on the load side occurs and persists The Eq 10 and Eq 11 are intended as a theoretical support to estimate the foldback curre...

Page 21: ...3 1 CVcc_3_btm 4 7 F capacitor 100 V 1812 TDK C4532X7S2A4 75M X7S 1812 4 1 CVcc_3 100 nF 100 V 1206 MULTICOMP MCCA000490 X7R 1206 5 1 Csns_3 1 F 10 V 0805 KEMET C0805C105K8 NACTU X8L 0805 6 1 Ccomp_3...

Page 22: ...IT Y RN73C2A2K61 BTDF 0805 18 1 Ruvlo_3 35 7 k 100 V 0 1 25 ppm C 0 100 W TE CONNECTIVIT Y RN73C2A35K7 BTDF 0805 19 1 Rcomp_3 1 k 0 1 25 ppm C 125 mW Panasonic ERA6AEB102V 0805 20 1 Rir_3 100 k 100 V...

Page 23: ...Revision history Table 7 Document revision history Date Version Changes 24 Jul 2019 1 Initial release UM2605 UM2605 Rev 1 page 23 27...

Page 24: ...and trip off time programming 7 3 3 1 Layout of the EVAL RHRICL1ATV1 board 9 3 3 2 Bill of material of the EVAL RHRICL1ATV1 board 10 4 Features EVAL RHRICL1ALV1 latched mode 12 4 1 Getting started 12...

Page 25: ...ools 2 Table 3 Signal on digital telemetry pin 4 Table 4 Bill of material 10 Table 5 Bill of material of the EVAL RHRICL1ALV1 board 15 Table 6 EVAL RHRICL1AFV1 bill of material 21 Table 7 Document rev...

Page 26: ...1ATV1 top layout 9 Figure 11 EVAL RHRICL1ATV1 bottom layout 9 Figure 12 Latched evaluation board schematic 12 Figure 13 Testing environment 13 Figure 14 Latched on at start up diagram 14 Figure 15 Lat...

Page 27: ...ts and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST pro...

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