PulseBlasterESR-PRO
Appendix I: Controlling the PulseBlasterESR-
PRO with SpinAPI
Instruction Set Architecture
Machine-Word Definition
The PulseBlasterESR-PRO pulse timing and control processor implements an 80-bit wide Very Long
Instruction Word (VLIW) architecture. The VLIW is partitioned into fields dedicated to specific purposes,
and every VLIW is viewed as a single instruction by the microcontroller. The maximum number of
instructions that can be loaded onto the PulseBlasterESR-PRO is 4096. The execution time of
instructions can be varied and is under (self) control by one of the fields of the instruction word – the
shortest being five clock cycles and the longest being 2
32
clock cycles.
Breakdown of 80-bit Instruction Word
All instructions have the same format and bit length, and all bit fields need to be filled. Table 4 shows
the fields and bit definitions of the 80-bit instruction word.
The 80-bit VLIW is broken up into 4 sections:
1. Output Pattern and Control Word: 24 bits.
2. Data Field: 20 bits.
3. OpCode: 4 bits.
4. Delay Count: 32 bits.
2019/09/26
Bit Definitions for the 80-bit Instruction Word (VLIW)
Output/Control Word
Data Field
OpCode
Delay Count
24 bits
20 bits
4 bits
32 bits
Table 4:
Partitioning of the 80-bit Instruction Word (VLIW).
